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StreamFMA_MAX5C_DFE_SIM
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Manager_StreamFMA_clockwidth.dot

Manager_StreamFMA_clockwidth.dot 3.8 KB
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  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. StreamFMAKernel_assign -> output_assign[color=green headport="assignment_2" tailport="assignment_10"];
    4. 

  4. StreamFMAKernel_assign -> a_assign[color=green headport="assignment_5" tailport="assignment_10"];
    5. 

  5. StreamFMAKernel_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_10" ROWSPAN="1" COLSPAN="1">6464 : width_in_a=32 width_in_b=32 width_out_output=32 clk=STREAM </TD></TR></TABLE>>];
    6. 

  6. StreamFMAKernel_assign -> StreamFMAKernel[color=gray];
    7. 

  7. a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    8. 

  8. a_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_5" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=PCIE </TD></TR></TABLE>>];
    9. 

  9. a_assign -> a[color=gray];
    10. 

  10. b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    11. 

  11. b_assign -> StreamFMAKernel_assign[color=green headport="assignment_10" tailport="assignment_13"];
    12. 

  12. b_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_13" ROWSPAN="1" COLSPAN="1">22592 : width=128 clk=PCIE </TD></TR></TABLE>>];
    13. 

  13. b_assign -> b[color=gray];
    14. 

  14. output[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : output</TD></TR></TABLE>>];
    15. 

  15. output_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_2" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=PCIE </TD></TR></TABLE>>];
    16. 

  16. output_assign -> output[color=gray];
    17. 

  17. a -> StreamFMAKernel [headport="a" tailport="a" label="{D{data:1}}"]
    18. 

  18. b -> StreamFMAKernel [headport="b" tailport="b" label="{D{data:1}}"]
    19. 

  19. StreamFMAKernel -> output [headport="output" tailport="output" label="{D{data:1}}"]
    20. 

  20. }
    21. 

  21.