digraph manager_compiler_graph { StreamFMAKernel[shape=plaintext, label=<

a
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2

b
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2

Kernel : StreamFMAKernel

output
clk=STREAM (100.0MHz)
width=32
PUSH 5

>]; StreamFMAKernel_assign -> output_assign[color=green headport="assignment_2" tailport="assignment_10"]; StreamFMAKernel_assign -> a_assign[color=green headport="assignment_5" tailport="assignment_10"]; StreamFMAKernel_assign[shape=plaintext, label=<

6464 : width_in_a=32 width_in_b=32 width_out_output=32 clk=STREAM

>]; StreamFMAKernel_assign -> StreamFMAKernel[color=gray]; a[shape=plaintext, label=<

PCIe_From_Host : a

a
clk=PCIE (125.0MHz)
width=128
PUSH 2

>]; a_assign[shape=plaintext, label=<

0 : width=128 clk=PCIE

>]; a_assign -> a[color=gray]; b[shape=plaintext, label=<

PCIe_From_Host : b

b
clk=PCIE (125.0MHz)
width=128
PUSH 2

>]; b_assign -> StreamFMAKernel_assign[color=green headport="assignment_10" tailport="assignment_13"]; b_assign[shape=plaintext, label=<

22592 : width=128 clk=PCIE

>]; b_assign -> b[color=gray]; output[shape=plaintext, label=<

output
clk=PCIE (125.0MHz)
width=128
PUSH 1

PCIe_To_Host : output

>]; output_assign[shape=plaintext, label=<

0 : width=128 clk=PCIE

>]; output_assign -> output[color=gray]; a -> StreamFMAKernel [headport="a" tailport="a" label="{D{data:1}}"] b -> StreamFMAKernel [headport="b" tailport="b" label="{D{data:1}}"] StreamFMAKernel -> output [headport="output" tailport="output" label="{D{data:1}}"] }