starpu_slu_lu_model_21.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 7372800 0.000000e+00 1.583302e+04 2.624137e+03 3.974089e+06 6.465024e+10 251
  37. 2c1922b7 819200 0.000000e+00 3.523655e+03 5.077738e+02 5.990214e+04 2.154576e+08 17
  38. d39bff17 3276800 0.000000e+00 8.986208e+03 1.629610e+03 1.797242e+05 1.668151e+09 20
  39. ####################
  40. # COMB_3
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 0
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda0_impl0 (Comb3)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 7372800 0.000000e+00 1.570696e+03 2.281691e+02 4.115224e+05 6.600167e+08 262
  68. 2c1922b7 819200 0.000000e+00 2.882912e+02 5.271451e+01 7.409085e+04 2.207390e+07 257
  69. d39bff17 3276800 0.000000e+00 8.365056e+02 1.344660e+02 1.396964e+05 1.198764e+08 167
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 2
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda2_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 7372800 0.000000e+00 1.571709e+03 2.150516e+02 4.007858e+05 6.417117e+08 255
  99. 2c1922b7 819200 0.000000e+00 9.967334e+01 2.197557e+01 2.372225e+04 2.479413e+06 238
  100. d39bff17 3276800 0.000000e+00 7.019049e+02 1.632697e+02 1.109010e+05 8.205375e+07 158
  101. ####################
  102. # COMB_0
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 3
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda3_impl0 (Comb0)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 7372800 0.000000e+00 1.569547e+03 2.419662e+02 2.589752e+05 4.161341e+08 165
  130. 2c1922b7 819200 0.000000e+00 2.858293e+02 5.241353e+01 7.460146e+04 2.204030e+07 261
  131. d39bff17 3276800 0.000000e+00 8.352707e+02 1.515223e+02 1.587014e+05 1.369209e+08 190
  132. ####################
  133. # COMB_1
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 1
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda1_impl0 (Comb1)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 7372800 0.000000e+00 1.591448e+03 2.256700e+02 2.387172e+05 3.875451e+08 150
  161. 2c1922b7 819200 0.000000e+00 2.930233e+02 5.590601e+01 5.362326e+04 1.628483e+07 183
  162. d39bff17 3276800 0.000000e+00 8.453596e+02 1.395049e+02 1.420204e+05 1.233279e+08 168