save_cl_bottom.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 4af260f6 14678040 0.000000e+00 3.447447e+01 7.398265e+00 3.237153e+04 1.167387e+06 939
  37. fb4b8624 4427800 0.000000e+00 5.439097e+01 1.253425e+01 3.094846e+05 1.772711e+07 5690
  38. f2ff9ae5 34480152 0.000000e+00 5.041329e+01 1.085485e+01 6.226042e+04 3.284270e+06 1235
  39. ####################
  40. # COMB_1
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb1)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 4af260f6 14678040 0.000000e+00 3.176283e+01 6.812714e+00 1.673901e+04 5.561382e+05 527
  68. fb4b8624 4427800 0.000000e+00 5.311651e+01 1.346481e+01 1.290731e+04 7.296474e+05 243
  69. f2ff9ae5 34480152 0.000000e+00 4.192896e+01 9.759572e+00 3.207566e+04 1.417765e+06 765
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 2
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda2_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 4af260f6 14678040 0.000000e+00 3.786531e+01 9.328071e+00 1.991715e+04 7.999380e+05 526
  99. fb4b8624 4427800 0.000000e+00 5.555598e+01 1.303330e+01 9.444517e+03 5.535768e+05 170
  100. f2ff9ae5 34480152 0.000000e+00 4.359390e+01 1.022197e+01 2.218929e+04 1.020503e+06 509
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 1
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda1_impl0 (Comb3)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 4af260f6 14678040 0.000000e+00 4.035980e+01 9.947105e+00 1.989738e+04 8.518341e+05 493
  130. fb4b8624 4427800 0.000000e+00 8.863692e+01 1.909792e+01 1.161144e+04 1.076982e+06 131
  131. f2ff9ae5 34480152 0.000000e+00 3.838146e+01 9.359960e+00 2.890124e+04 1.175241e+06 753
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 4af260f6 14678040 0.000000e+00 3.505264e+01 8.845541e+00 1.945422e+04 7.253469e+05 555
  161. fb4b8624 4427800 0.000000e+00 4.717545e+01 1.027132e+01 6.227160e+03 3.076951e+05 132
  162. f2ff9ae5 34480152 0.000000e+00 3.110432e+01 6.170515e+00 2.370149e+04 7.662320e+05 762