Главная Обзор Помощь
Вход
exa2pro
/
starpu-max
Следить 19
В избранное 0
Ответвить 0
Файлы Обсуждения 0 Запросы на слияние 0 Вики
Дерево: 3adbf06fc7
Ветки Метки
starpu-max
/
tests
/
StreamFMA_MAX5C_DFE_SIM
/
scratch
/
Manager_StreamFMA_clockwidth.dot

Manager_StreamFMA_clockwidth.dot 39 KB
История Исходник

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140 
  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT2" ROWSPAN="1" COLSPAN="1">inAT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT2" ROWSPAN="1" COLSPAN="1">inBT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT3" ROWSPAN="1" COLSPAN="1">inAT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT3" ROWSPAN="1" COLSPAN="1">inBT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT1" ROWSPAN="1" COLSPAN="1">oDataT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT2" ROWSPAN="1" COLSPAN="1">oDataT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. StreamFMAKernel_assign -> oDataT3_assign[color=green headport="assignment_221" tailport="assignment_238"];
    4. 

  4. StreamFMAKernel_assign -> inAT1_assign[color=green headport="assignment_224" tailport="assignment_238"];
    5. 

  5. StreamFMAKernel_assign -> inBT1_assign[color=green headport="assignment_227" tailport="assignment_238"];
    6. 

  6. StreamFMAKernel_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_238" ROWSPAN="1" COLSPAN="1">9696 : width_in_inAT1=32 width_in_inBT1=32 width_in_inAT2=32 width_in_inBT2=32 width_in_inAT3=32 width_in_inBT3=32 width_out_oDataT1=32 width_out_oDataT2=32 width_out_oDataT3=32 clk=STREAM </TD></TR></TABLE>>];
    7. 

  7. StreamFMAKernel_assign -> StreamFMAKernel[color=gray];
    8. 

  8. inAT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inAT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    9. 

  9. inAT1_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_224" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=PCIE </TD></TR></TABLE>>];
    10. 

  10. inAT1_assign -> inAT1[color=gray];
    11. 

  11. inBT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inBT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    12. 

  12. inBT1_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_227" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=PCIE </TD></TR></TABLE>>];
    13. 

  13. inBT1_assign -> inBT1[color=gray];
    14. 

  14. oDataT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : oDataT3</TD></TR></TABLE>>];
    15. 

  15. oDataT3_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_221" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=PCIE </TD></TR></TABLE>>];
    16. 

  16. oDataT3_assign -> oDataT3[color=gray];
    17. 

  17. MemoryControllerPro0[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_a" ROWSPAN="1" COLSPAN="1">read_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_b" ROWSPAN="1" COLSPAN="1">read_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_c" ROWSPAN="1" COLSPAN="1">read_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_0" ROWSPAN="1" COLSPAN="1">read_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_1" ROWSPAN="1" COLSPAN="1">read_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_2" ROWSPAN="1" COLSPAN="1">read_command_2<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_3" ROWSPAN="1" COLSPAN="1">read_command_3<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_0" ROWSPAN="1" COLSPAN="1">write_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_1" ROWSPAN="1" COLSPAN="1">write_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_0" ROWSPAN="1" COLSPAN="1">write_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_1" ROWSPAN="1" COLSPAN="1">write_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_MemoryControllerPro0 : MemoryControllerPro0</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_0" ROWSPAN="1" COLSPAN="1">read_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_1" ROWSPAN="1" COLSPAN="1">read_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_2" ROWSPAN="1" COLSPAN="1">read_2<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_3" ROWSPAN="1" COLSPAN="1">read_3<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="Tag_Out" ROWSPAN="1" COLSPAN="1">Tag_Out<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_a" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_b" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_c" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR></TABLE>>];
    18. 

  18. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    19. 

  19. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    20. 

  20. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    21. 

  21. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    22. 

  22. MemoryControllerPro0_assign -> MemoryControllerPro0_IntSource_assign[color=green headport="assignment_47" tailport="assignment_267"];
    23. 

  23. MemoryControllerPro0_assign -> Stream_33_pipeline_4_assign[color=green headport="assignment_111" tailport="assignment_267"];
    24. 

  24. MemoryControllerPro0_assign -> Stream_28_pipeline_4_assign[color=green headport="assignment_145" tailport="assignment_267"];
    25. 

  25. MemoryControllerPro0_assign -> Stream_38_pipeline_4_assign[color=green headport="assignment_179" tailport="assignment_267"];
    26. 

  26. MemoryControllerPro0_assign -> Stream_34_pipeline_4_assign[color=green headport="assignment_126" tailport="assignment_267"];
    27. 

  27. MemoryControllerPro0_assign -> Stream_29_pipeline_4_assign[color=green headport="assignment_160" tailport="assignment_267"];
    28. 

  28. MemoryControllerPro0_assign -> Stream_39_pipeline_4_assign[color=green headport="assignment_194" tailport="assignment_267"];
    29. 

  29. MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inAT2_assign[color=green headport="assignment_201" tailport="assignment_267"];
    30. 

  30. MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inAT3_assign[color=green headport="assignment_204" tailport="assignment_267"];
    31. 

  31. MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inBT3_assign[color=green headport="assignment_207" tailport="assignment_267"];
    32. 

  32. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    33. 

  33. MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"];
    34. 

  34. MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_oDataT1_assign[color=green headport="assignment_241" tailport="assignment_267"];
    35. 

  35. MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_oDataT2_assign[color=green headport="assignment_244" tailport="assignment_267"];
    36. 

  36. MemoryControllerPro0_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_267" ROWSPAN="1" COLSPAN="1">983264 : read_stream_maxj_a=512 read_stream_maxj_b=512 read_stream_maxj_c=512 read_0=1536 read_1=1536 read_2=1536 read_3=1536 read_command_0=64 read_command_1=64 read_command_2=64 read_command_3=64 write_0=1536 write_1=1536 write_command_0=64 write_command_1=64 Tag_Out=1 cmd_stream_maxj_a=544 cmd_stream_maxj_b=544 cmd_stream_maxj_c=544 clk=STREAM clk_MemoryControllerPro0_clk=MemoryControllerPro0_clk clk_STREAM=STREAM </TD></TR></TABLE>>];
    37. 

  37. MemoryControllerPro0_assign -> MemoryControllerPro0[color=gray];
    38. 

  38. MemoryControllerPro0_IntSource[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="Tag_In" ROWSPAN="1" COLSPAN="1">Tag_In<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryInterruptSource : MemoryControllerPro0_IntSource</TD></TR></TABLE>>];
    39. 

  39. MemoryControllerPro0_IntSource_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_46" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=STREAM </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_47" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_48" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=PCIE </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_49" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_50" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_51" ROWSPAN="1" COLSPAN="1">0 : tag_in=1 clk=DDR_CLK_c </TD></TR></TABLE>>];
    40. 

  40. MemoryControllerPro0_IntSource_assign -> MemoryControllerPro0_IntSource[color=gray];
    41. 

  41. MemoryControllerInterface_b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_b : MemoryControllerInterface_b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    42. 

  42. MemoryControllerInterface_b_assign -> Stream_28_pipeline_4_assign[color=green headport="assignment_145" tailport="assignment_149"];
    43. 

  43. MemoryControllerInterface_b_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_149" ROWSPAN="1" COLSPAN="1">544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_b=DDR_CLK_b </TD></TR></TABLE>>];
    44. 

  44. MemoryControllerInterface_b_assign -> MemoryControllerInterface_b[color=gray];
    45. 

  45. MemoryControllerInterface_a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_a : MemoryControllerInterface_a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    46. 

  46. MemoryControllerInterface_a_assign -> Stream_33_pipeline_4_assign[color=green headport="assignment_111" tailport="assignment_115"];
    47. 

  47. MemoryControllerInterface_a_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_115" ROWSPAN="1" COLSPAN="1">544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_a=DDR_CLK_a </TD></TR></TABLE>>];
    48. 

  48. MemoryControllerInterface_a_assign -> MemoryControllerInterface_a[color=gray];
    49. 

  49. MemoryControllerInterface_c[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_c : MemoryControllerInterface_c</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    50. 

  50. MemoryControllerInterface_c_assign -> Stream_38_pipeline_4_assign[color=green headport="assignment_179" tailport="assignment_183"];
    51. 

  51. MemoryControllerInterface_c_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_183" ROWSPAN="1" COLSPAN="1">544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_c=DDR_CLK_c </TD></TR></TABLE>>];
    52. 

  52. MemoryControllerInterface_c_assign -> MemoryControllerInterface_c[color=gray];
    53. 

  53. addrgen_cmd_MemoryControllerPro0_inAT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2 : addrgen_cmd_MemoryControllerPro0_inAT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    54. 

  54. addrgen_cmd_MemoryControllerPro0_inAT2_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_201" ROWSPAN="1" COLSPAN="1">0 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    55. 

  55. addrgen_cmd_MemoryControllerPro0_inAT2_assign -> addrgen_cmd_MemoryControllerPro0_inAT2[color=gray];
    56. 

  56. addrgen_cmd_MemoryControllerPro0_inBT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2 : addrgen_cmd_MemoryControllerPro0_inBT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    57. 

  57. addrgen_cmd_MemoryControllerPro0_inBT2_assign -> MemoryControllerPro0_assign[color=green headport="assignment_267" tailport="assignment_270"];
    58. 

  58. addrgen_cmd_MemoryControllerPro0_inBT2_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_270" ROWSPAN="1" COLSPAN="1">983328 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    59. 

  59. addrgen_cmd_MemoryControllerPro0_inBT2_assign -> addrgen_cmd_MemoryControllerPro0_inBT2[color=gray];
    60. 

  60. addrgen_cmd_MemoryControllerPro0_inAT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3 : addrgen_cmd_MemoryControllerPro0_inAT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    61. 

  61. addrgen_cmd_MemoryControllerPro0_inAT3_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_204" ROWSPAN="1" COLSPAN="1">0 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    62. 

  62. addrgen_cmd_MemoryControllerPro0_inAT3_assign -> addrgen_cmd_MemoryControllerPro0_inAT3[color=gray];
    63. 

  63. addrgen_cmd_MemoryControllerPro0_inBT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3 : addrgen_cmd_MemoryControllerPro0_inBT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    64. 

  64. addrgen_cmd_MemoryControllerPro0_inBT3_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_207" ROWSPAN="1" COLSPAN="1">0 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    65. 

  65. addrgen_cmd_MemoryControllerPro0_inBT3_assign -> addrgen_cmd_MemoryControllerPro0_inBT3[color=gray];
    66. 

  66. addrgen_cmd_MemoryControllerPro0_oDataT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1 : addrgen_cmd_MemoryControllerPro0_oDataT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    67. 

  67. addrgen_cmd_MemoryControllerPro0_oDataT1_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_241" ROWSPAN="1" COLSPAN="1">0 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    68. 

  68. addrgen_cmd_MemoryControllerPro0_oDataT1_assign -> addrgen_cmd_MemoryControllerPro0_oDataT1[color=gray];
    69. 

  69. addrgen_cmd_MemoryControllerPro0_oDataT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2 : addrgen_cmd_MemoryControllerPro0_oDataT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    70. 

  70. addrgen_cmd_MemoryControllerPro0_oDataT2_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_244" ROWSPAN="1" COLSPAN="1">0 : cgen_out_0=64 clk=STREAM </TD></TR></TABLE>>];
    71. 

  71. addrgen_cmd_MemoryControllerPro0_oDataT2_assign -> addrgen_cmd_MemoryControllerPro0_oDataT2[color=gray];
    72. 

  72. Stream_34_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_34_pipeline : Stream_34_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    73. 

  73. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_124"];
    74. 

  74. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_125"];
    75. 

  75. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=green headport="assignment_115" tailport="assignment_126"];
    76. 

  76. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_127"];
    77. 

  77. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_128"];
    78. 

  78. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_129"];
    79. 

  79. Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_130"];
    80. 

  80. Stream_34_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_124" ROWSPAN="1" COLSPAN="1">9056 : width=32 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_125" ROWSPAN="1" COLSPAN="1">34592 : width=128 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_126" ROWSPAN="1" COLSPAN="1">544 : width=512 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_127" ROWSPAN="1" COLSPAN="1">409120 : width=1536 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_128" ROWSPAN="1" COLSPAN="1">17568 : width=64 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_129" ROWSPAN="1" COLSPAN="1">810 : width=1 clk=DDR_CLK_a </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_130" ROWSPAN="1" COLSPAN="1">145248 : width=544 clk=DDR_CLK_a </TD></TR></TABLE>>];
    81. 

  81. Stream_34_pipeline_4_assign -> Stream_34_pipeline_4[color=gray];
    82. 

  82. Stream_29_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_29_pipeline : Stream_29_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    83. 

  83. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_158"];
    84. 

  84. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_159"];
    85. 

  85. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=green headport="assignment_149" tailport="assignment_160"];
    86. 

  86. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_161"];
    87. 

  87. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_162"];
    88. 

  88. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_163"];
    89. 

  89. Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_164"];
    90. 

  90. Stream_29_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_158" ROWSPAN="1" COLSPAN="1">9056 : width=32 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_159" ROWSPAN="1" COLSPAN="1">34592 : width=128 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_160" ROWSPAN="1" COLSPAN="1">544 : width=512 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_161" ROWSPAN="1" COLSPAN="1">409120 : width=1536 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_162" ROWSPAN="1" COLSPAN="1">17568 : width=64 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_163" ROWSPAN="1" COLSPAN="1">810 : width=1 clk=DDR_CLK_b </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_164" ROWSPAN="1" COLSPAN="1">145248 : width=544 clk=DDR_CLK_b </TD></TR></TABLE>>];
    91. 

  91. Stream_29_pipeline_4_assign -> Stream_29_pipeline_4[color=gray];
    92. 

  92. Stream_39_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_39_pipeline : Stream_39_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    93. 

  93. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_192"];
    94. 

  94. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_193"];
    95. 

  95. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=green headport="assignment_183" tailport="assignment_194"];
    96. 

  96. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_195"];
    97. 

  97. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_196"];
    98. 

  98. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_197"];
    99. 

  99. Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_198"];
    100. 

  100. Stream_39_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_192" ROWSPAN="1" COLSPAN="1">9056 : width=32 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_193" ROWSPAN="1" COLSPAN="1">34592 : width=128 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_194" ROWSPAN="1" COLSPAN="1">544 : width=512 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_195" ROWSPAN="1" COLSPAN="1">409120 : width=1536 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_196" ROWSPAN="1" COLSPAN="1">17568 : width=64 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_197" ROWSPAN="1" COLSPAN="1">810 : width=1 clk=DDR_CLK_c </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_198" ROWSPAN="1" COLSPAN="1">145248 : width=544 clk=DDR_CLK_c </TD></TR></TABLE>>];
    101. 

  101. Stream_39_pipeline_4_assign -> Stream_39_pipeline_4[color=gray];
    102. 

  102. Stream_28_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_28_pipeline : Stream_28_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    103. 

  103. Stream_28_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_139" ROWSPAN="1" COLSPAN="1">0 : width=32 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_140" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_141" ROWSPAN="1" COLSPAN="1">0 : width=512 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_142" ROWSPAN="1" COLSPAN="1">0 : width=1536 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_143" ROWSPAN="1" COLSPAN="1">0 : width=64 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_144" ROWSPAN="1" COLSPAN="1">0 : width=1 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_145" ROWSPAN="1" COLSPAN="1">0 : width=544 clk=MemoryControllerPro0_clk </TD></TR></TABLE>>];
    104. 

  104. Stream_28_pipeline_4_assign -> Stream_28_pipeline_4[color=gray];
    105. 

  105. Stream_33_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_33_pipeline : Stream_33_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    106. 

  106. Stream_33_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_105" ROWSPAN="1" COLSPAN="1">0 : width=32 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_106" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_107" ROWSPAN="1" COLSPAN="1">0 : width=512 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_108" ROWSPAN="1" COLSPAN="1">0 : width=1536 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_109" ROWSPAN="1" COLSPAN="1">0 : width=64 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_110" ROWSPAN="1" COLSPAN="1">0 : width=1 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_111" ROWSPAN="1" COLSPAN="1">0 : width=544 clk=MemoryControllerPro0_clk </TD></TR></TABLE>>];
    107. 

  107. Stream_33_pipeline_4_assign -> Stream_33_pipeline_4[color=gray];
    108. 

  108. Stream_38_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_38_pipeline : Stream_38_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    109. 

  109. Stream_38_pipeline_4_assign[shape=plaintext, label=<<TABLE  BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_173" ROWSPAN="1" COLSPAN="1">0 : width=32 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_174" ROWSPAN="1" COLSPAN="1">0 : width=128 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_175" ROWSPAN="1" COLSPAN="1">0 : width=512 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_176" ROWSPAN="1" COLSPAN="1">0 : width=1536 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_177" ROWSPAN="1" COLSPAN="1">0 : width=64 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="white" BORDER="1" PORT="assignment_178" ROWSPAN="1" COLSPAN="1">0 : width=1 clk=MemoryControllerPro0_clk </TD></TR><TR><TD BGCOLOR="green" BORDER="1" PORT="assignment_179" ROWSPAN="1" COLSPAN="1">0 : width=544 clk=MemoryControllerPro0_clk </TD></TR></TABLE>>];
    110. 

  110. Stream_38_pipeline_4_assign -> Stream_38_pipeline_4[color=gray];
    111. 

  111. inAT1 -> StreamFMAKernel [headport="inAT1" tailport="inAT1" label="{D{data:1}}"]
    112. 

  112. inBT1 -> StreamFMAKernel [headport="inBT1" tailport="inBT1" label="{D{data:1}}"]
    113. 

  113. StreamFMAKernel -> MemoryControllerPro0 [headport="write_0" tailport="oDataT1" label="{D{data:1}}"]
    114. 

  114. StreamFMAKernel -> MemoryControllerPro0 [headport="write_1" tailport="oDataT2" label="{D{data:1}}"]
    115. 

  115. StreamFMAKernel -> oDataT3 [headport="oDataT3" tailport="oDataT3" label="{D{data:1}}"]
    116. 

  116. MemoryControllerPro0 -> MemoryControllerPro0_IntSource [headport="Tag_In" tailport="Tag_Out" label="{D{data:1}}"]
    117. 

  117. MemoryControllerPro0 -> Stream_28_pipeline_4 [headport="input" tailport="cmd_stream_maxj_b" label="{D{data:1}}"]
    118. 

  118. MemoryControllerInterface_b -> Stream_29_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    119. 

  119. MemoryControllerPro0 -> Stream_33_pipeline_4 [headport="input" tailport="cmd_stream_maxj_a" label="{D{data:1}}"]
    120. 

  120. MemoryControllerInterface_a -> Stream_34_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    121. 

  121. MemoryControllerPro0 -> Stream_38_pipeline_4 [headport="input" tailport="cmd_stream_maxj_c" label="{D{data:1}}"]
    122. 

  122. MemoryControllerInterface_c -> Stream_39_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    123. 

  123. addrgen_cmd_MemoryControllerPro0_inAT2 -> MemoryControllerPro0 [headport="read_command_0" tailport="cgen_out_0" label="{D{data:1}}"]
    124. 

  124. MemoryControllerPro0 -> StreamFMAKernel [headport="inAT2" tailport="read_0" label="{D{data:1}}"]
    125. 

  125. addrgen_cmd_MemoryControllerPro0_inBT2 -> MemoryControllerPro0 [headport="read_command_1" tailport="cgen_out_0" label="{D{data:1}}"]
    126. 

  126. MemoryControllerPro0 -> StreamFMAKernel [headport="inBT2" tailport="read_1" label="{D{data:1}}"]
    127. 

  127. addrgen_cmd_MemoryControllerPro0_inAT3 -> MemoryControllerPro0 [headport="read_command_2" tailport="cgen_out_0" label="{D{data:1}}"]
    128. 

  128. MemoryControllerPro0 -> StreamFMAKernel [headport="inAT3" tailport="read_2" label="{D{data:1}}"]
    129. 

  129. addrgen_cmd_MemoryControllerPro0_inBT3 -> MemoryControllerPro0 [headport="read_command_3" tailport="cgen_out_0" label="{D{data:1}}"]
    130. 

  130. MemoryControllerPro0 -> StreamFMAKernel [headport="inBT3" tailport="read_3" label="{D{data:1}}"]
    131. 

  131. addrgen_cmd_MemoryControllerPro0_oDataT1 -> MemoryControllerPro0 [headport="write_command_0" tailport="cgen_out_0" label="{D{data:1}}"]
    132. 

  132. addrgen_cmd_MemoryControllerPro0_oDataT2 -> MemoryControllerPro0 [headport="write_command_1" tailport="cgen_out_0" label="{D{data:1}}"]
    133. 

  133. Stream_34_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_a" tailport="output" label="{D{data:1}}"]
    134. 

  134. Stream_29_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_b" tailport="output" label="{D{data:1}}"]
    135. 

  135. Stream_39_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_c" tailport="output" label="{D{data:1}}"]
    136. 

  136. Stream_28_pipeline_4 -> MemoryControllerInterface_b [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    137. 

  137. Stream_33_pipeline_4 -> MemoryControllerInterface_a [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    138. 

  138. Stream_38_pipeline_4 -> MemoryControllerInterface_c [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    139. 

  139. }
    140. 

  140.