digraph manager_compiler_graph { StreamFMAKernel[shape=plaintext, label=<
inAT1
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT1
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inAT2
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT2
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inAT3
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT3
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2
Kernel : StreamFMAKernel
oDataT1
clk=STREAM (100.0MHz)
width=32
PUSH 5		oDataT2
clk=STREAM (100.0MHz)
width=32
PUSH 5		oDataT3
clk=STREAM (100.0MHz)
width=32
PUSH 5
>]; StreamFMAKernel_assign -> oDataT3_assign[color=green headport="assignment_221" tailport="assignment_238"]; StreamFMAKernel_assign -> inAT1_assign[color=green headport="assignment_224" tailport="assignment_238"]; StreamFMAKernel_assign -> inBT1_assign[color=green headport="assignment_227" tailport="assignment_238"]; StreamFMAKernel_assign[shape=plaintext, label=<
9696 : width_in_inAT1=32 width_in_inBT1=32 width_in_inAT2=32 width_in_inBT2=32 width_in_inAT3=32 width_in_inBT3=32 width_out_oDataT1=32 width_out_oDataT2=32 width_out_oDataT3=32 clk=STREAM
>]; StreamFMAKernel_assign -> StreamFMAKernel[color=gray]; inAT1[shape=plaintext, label=<
PCIe_From_Host : inAT1
inAT1
clk=PCIE (125.0MHz)
width=128
PUSH 2
>]; inAT1_assign[shape=plaintext, label=<
0 : width=128 clk=PCIE
>]; inAT1_assign -> inAT1[color=gray]; inBT1[shape=plaintext, label=<
PCIe_From_Host : inBT1
inBT1
clk=PCIE (125.0MHz)
width=128
PUSH 2
>]; inBT1_assign[shape=plaintext, label=<
0 : width=128 clk=PCIE
>]; inBT1_assign -> inBT1[color=gray]; oDataT3[shape=plaintext, label=<
oDataT3
clk=PCIE (125.0MHz)
width=128
PUSH 1
PCIe_To_Host : oDataT3
>]; oDataT3_assign[shape=plaintext, label=<
0 : width=128 clk=PCIE
>]; oDataT3_assign -> oDataT3[color=gray]; MemoryControllerPro0[shape=plaintext, label=<
read_stream_maxj_a
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_stream_maxj_b
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_stream_maxj_c
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_command_0
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_1
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_2
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_3
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		write_0
clk=STREAM (100.0MHz)
width=1536
PUSH 8		write_1
clk=STREAM (100.0MHz)
width=1536
PUSH 8		write_command_0
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		write_command_1
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8
ManagerStateMachine_MemoryControllerPro0 : MemoryControllerPro0
read_0
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_1
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_2
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_3
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		Tag_Out
clk=MemoryControllerPro0_clk (272.5MHz)
width=1
PUSH 1		cmd_stream_maxj_a
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3		cmd_stream_maxj_b
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3		cmd_stream_maxj_c
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3
>]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> MemoryControllerPro0_IntSource_assign[color=green headport="assignment_47" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_33_pipeline_4_assign[color=green headport="assignment_111" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_28_pipeline_4_assign[color=green headport="assignment_145" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_38_pipeline_4_assign[color=green headport="assignment_179" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_34_pipeline_4_assign[color=green headport="assignment_126" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_29_pipeline_4_assign[color=green headport="assignment_160" tailport="assignment_267"]; MemoryControllerPro0_assign -> Stream_39_pipeline_4_assign[color=green headport="assignment_194" tailport="assignment_267"]; MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inAT2_assign[color=green headport="assignment_201" tailport="assignment_267"]; MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inAT3_assign[color=green headport="assignment_204" tailport="assignment_267"]; MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_inBT3_assign[color=green headport="assignment_207" tailport="assignment_267"]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> StreamFMAKernel_assign[color=green headport="assignment_238" tailport="assignment_267"]; MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_oDataT1_assign[color=green headport="assignment_241" tailport="assignment_267"]; MemoryControllerPro0_assign -> addrgen_cmd_MemoryControllerPro0_oDataT2_assign[color=green headport="assignment_244" tailport="assignment_267"]; MemoryControllerPro0_assign[shape=plaintext, label=<
983264 : read_stream_maxj_a=512 read_stream_maxj_b=512 read_stream_maxj_c=512 read_0=1536 read_1=1536 read_2=1536 read_3=1536 read_command_0=64 read_command_1=64 read_command_2=64 read_command_3=64 write_0=1536 write_1=1536 write_command_0=64 write_command_1=64 Tag_Out=1 cmd_stream_maxj_a=544 cmd_stream_maxj_b=544 cmd_stream_maxj_c=544 clk=STREAM clk_MemoryControllerPro0_clk=MemoryControllerPro0_clk clk_STREAM=STREAM
>]; MemoryControllerPro0_assign -> MemoryControllerPro0[color=gray]; MemoryControllerPro0_IntSource[shape=plaintext, label=<
Tag_In
clk=MemoryControllerPro0_clk (272.5MHz)
width=1
PUSH 1
MemoryInterruptSource : MemoryControllerPro0_IntSource
>]; MemoryControllerPro0_IntSource_assign[shape=plaintext, label=<
0 : tag_in=1 clk=STREAM
0 : tag_in=1 clk=MemoryControllerPro0_clk
0 : tag_in=1 clk=PCIE
0 : tag_in=1 clk=DDR_CLK_b
0 : tag_in=1 clk=DDR_CLK_a
0 : tag_in=1 clk=DDR_CLK_c
>]; MemoryControllerPro0_IntSource_assign -> MemoryControllerPro0_IntSource[color=gray]; MemoryControllerInterface_b[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_b (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_b : MemoryControllerInterface_b
read_stream_maxj
clk=DDR_CLK_b (266.6MHz)
width=512
PUSH 1
>]; MemoryControllerInterface_b_assign -> Stream_28_pipeline_4_assign[color=green headport="assignment_145" tailport="assignment_149"]; MemoryControllerInterface_b_assign[shape=plaintext, label=<
544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_b=DDR_CLK_b
>]; MemoryControllerInterface_b_assign -> MemoryControllerInterface_b[color=gray]; MemoryControllerInterface_a[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_a (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_a : MemoryControllerInterface_a
read_stream_maxj
clk=DDR_CLK_a (266.6MHz)
width=512
PUSH 1
>]; MemoryControllerInterface_a_assign -> Stream_33_pipeline_4_assign[color=green headport="assignment_111" tailport="assignment_115"]; MemoryControllerInterface_a_assign[shape=plaintext, label=<
544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_a=DDR_CLK_a
>]; MemoryControllerInterface_a_assign -> MemoryControllerInterface_a[color=gray]; MemoryControllerInterface_c[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_c (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_c : MemoryControllerInterface_c
read_stream_maxj
clk=DDR_CLK_c (266.6MHz)
width=512
PUSH 1
>]; MemoryControllerInterface_c_assign -> Stream_38_pipeline_4_assign[color=green headport="assignment_179" tailport="assignment_183"]; MemoryControllerInterface_c_assign[shape=plaintext, label=<
544 : cmd_stream_maxj=544 read_stream_maxj=512 DDR_CLK_c=DDR_CLK_c
>]; MemoryControllerInterface_c_assign -> MemoryControllerInterface_c[color=gray]; addrgen_cmd_MemoryControllerPro0_inAT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2 : addrgen_cmd_MemoryControllerPro0_inAT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inAT2_assign[shape=plaintext, label=<
0 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_inAT2_assign -> addrgen_cmd_MemoryControllerPro0_inAT2[color=gray]; addrgen_cmd_MemoryControllerPro0_inBT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2 : addrgen_cmd_MemoryControllerPro0_inBT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inBT2_assign -> MemoryControllerPro0_assign[color=green headport="assignment_267" tailport="assignment_270"]; addrgen_cmd_MemoryControllerPro0_inBT2_assign[shape=plaintext, label=<
983328 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_inBT2_assign -> addrgen_cmd_MemoryControllerPro0_inBT2[color=gray]; addrgen_cmd_MemoryControllerPro0_inAT3[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3 : addrgen_cmd_MemoryControllerPro0_inAT3
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inAT3_assign[shape=plaintext, label=<
0 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_inAT3_assign -> addrgen_cmd_MemoryControllerPro0_inAT3[color=gray]; addrgen_cmd_MemoryControllerPro0_inBT3[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3 : addrgen_cmd_MemoryControllerPro0_inBT3
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inBT3_assign[shape=plaintext, label=<
0 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_inBT3_assign -> addrgen_cmd_MemoryControllerPro0_inBT3[color=gray]; addrgen_cmd_MemoryControllerPro0_oDataT1[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1 : addrgen_cmd_MemoryControllerPro0_oDataT1
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_oDataT1_assign[shape=plaintext, label=<
0 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_oDataT1_assign -> addrgen_cmd_MemoryControllerPro0_oDataT1[color=gray]; addrgen_cmd_MemoryControllerPro0_oDataT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2 : addrgen_cmd_MemoryControllerPro0_oDataT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_oDataT2_assign[shape=plaintext, label=<
0 : cgen_out_0=64 clk=STREAM
>]; addrgen_cmd_MemoryControllerPro0_oDataT2_assign -> addrgen_cmd_MemoryControllerPro0_oDataT2[color=gray]; Stream_34_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_a (266.6MHz)
width=512
PUSH 1
Stream_34_pipeline : Stream_34_pipeline_4
output
clk=DDR_CLK_a (266.6MHz)
width=512
PUSH 9
>]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_124"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_125"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=green headport="assignment_115" tailport="assignment_126"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_127"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_128"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_129"]; Stream_34_pipeline_4_assign -> MemoryControllerInterface_a_assign[color=gray63 headport="assignment_115" tailport="assignment_130"]; Stream_34_pipeline_4_assign[shape=plaintext, label=<
9056 : width=32 clk=DDR_CLK_a
34592 : width=128 clk=DDR_CLK_a
544 : width=512 clk=DDR_CLK_a
409120 : width=1536 clk=DDR_CLK_a
17568 : width=64 clk=DDR_CLK_a
810 : width=1 clk=DDR_CLK_a
145248 : width=544 clk=DDR_CLK_a
>]; Stream_34_pipeline_4_assign -> Stream_34_pipeline_4[color=gray]; Stream_29_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_b (266.6MHz)
width=512
PUSH 1
Stream_29_pipeline : Stream_29_pipeline_4
output
clk=DDR_CLK_b (266.6MHz)
width=512
PUSH 9
>]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_158"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_159"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=green headport="assignment_149" tailport="assignment_160"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_161"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_162"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_163"]; Stream_29_pipeline_4_assign -> MemoryControllerInterface_b_assign[color=gray63 headport="assignment_149" tailport="assignment_164"]; Stream_29_pipeline_4_assign[shape=plaintext, label=<
9056 : width=32 clk=DDR_CLK_b
34592 : width=128 clk=DDR_CLK_b
544 : width=512 clk=DDR_CLK_b
409120 : width=1536 clk=DDR_CLK_b
17568 : width=64 clk=DDR_CLK_b
810 : width=1 clk=DDR_CLK_b
145248 : width=544 clk=DDR_CLK_b
>]; Stream_29_pipeline_4_assign -> Stream_29_pipeline_4[color=gray]; Stream_39_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_c (266.6MHz)
width=512
PUSH 1
Stream_39_pipeline : Stream_39_pipeline_4
output
clk=DDR_CLK_c (266.6MHz)
width=512
PUSH 9
>]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_192"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_193"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=green headport="assignment_183" tailport="assignment_194"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_195"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_196"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_197"]; Stream_39_pipeline_4_assign -> MemoryControllerInterface_c_assign[color=gray63 headport="assignment_183" tailport="assignment_198"]; Stream_39_pipeline_4_assign[shape=plaintext, label=<
9056 : width=32 clk=DDR_CLK_c
34592 : width=128 clk=DDR_CLK_c
544 : width=512 clk=DDR_CLK_c
409120 : width=1536 clk=DDR_CLK_c
17568 : width=64 clk=DDR_CLK_c
810 : width=1 clk=DDR_CLK_c
145248 : width=544 clk=DDR_CLK_c
>]; Stream_39_pipeline_4_assign -> Stream_39_pipeline_4[color=gray]; Stream_28_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3
Stream_28_pipeline : Stream_28_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 11
>]; Stream_28_pipeline_4_assign[shape=plaintext, label=<
0 : width=32 clk=MemoryControllerPro0_clk
0 : width=128 clk=MemoryControllerPro0_clk
0 : width=512 clk=MemoryControllerPro0_clk
0 : width=1536 clk=MemoryControllerPro0_clk
0 : width=64 clk=MemoryControllerPro0_clk
0 : width=1 clk=MemoryControllerPro0_clk
0 : width=544 clk=MemoryControllerPro0_clk
>]; Stream_28_pipeline_4_assign -> Stream_28_pipeline_4[color=gray]; Stream_33_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3
Stream_33_pipeline : Stream_33_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 11
>]; Stream_33_pipeline_4_assign[shape=plaintext, label=<
0 : width=32 clk=MemoryControllerPro0_clk
0 : width=128 clk=MemoryControllerPro0_clk
0 : width=512 clk=MemoryControllerPro0_clk
0 : width=1536 clk=MemoryControllerPro0_clk
0 : width=64 clk=MemoryControllerPro0_clk
0 : width=1 clk=MemoryControllerPro0_clk
0 : width=544 clk=MemoryControllerPro0_clk
>]; Stream_33_pipeline_4_assign -> Stream_33_pipeline_4[color=gray]; Stream_38_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3
Stream_38_pipeline : Stream_38_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 11
>]; Stream_38_pipeline_4_assign[shape=plaintext, label=<
0 : width=32 clk=MemoryControllerPro0_clk
0 : width=128 clk=MemoryControllerPro0_clk
0 : width=512 clk=MemoryControllerPro0_clk
0 : width=1536 clk=MemoryControllerPro0_clk
0 : width=64 clk=MemoryControllerPro0_clk
0 : width=1 clk=MemoryControllerPro0_clk
0 : width=544 clk=MemoryControllerPro0_clk
>]; Stream_38_pipeline_4_assign -> Stream_38_pipeline_4[color=gray]; inAT1 -> StreamFMAKernel [headport="inAT1" tailport="inAT1" label="{D{data:1}}"] inBT1 -> StreamFMAKernel [headport="inBT1" tailport="inBT1" label="{D{data:1}}"] StreamFMAKernel -> MemoryControllerPro0 [headport="write_0" tailport="oDataT1" label="{D{data:1}}"] StreamFMAKernel -> MemoryControllerPro0 [headport="write_1" tailport="oDataT2" label="{D{data:1}}"] StreamFMAKernel -> oDataT3 [headport="oDataT3" tailport="oDataT3" label="{D{data:1}}"] MemoryControllerPro0 -> MemoryControllerPro0_IntSource [headport="Tag_In" tailport="Tag_Out" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_28_pipeline_4 [headport="input" tailport="cmd_stream_maxj_b" label="{D{data:1}}"] MemoryControllerInterface_b -> Stream_29_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_33_pipeline_4 [headport="input" tailport="cmd_stream_maxj_a" label="{D{data:1}}"] MemoryControllerInterface_a -> Stream_34_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_38_pipeline_4 [headport="input" tailport="cmd_stream_maxj_c" label="{D{data:1}}"] MemoryControllerInterface_c -> Stream_39_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inAT2 -> MemoryControllerPro0 [headport="read_command_0" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inAT2" tailport="read_0" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inBT2 -> MemoryControllerPro0 [headport="read_command_1" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inBT2" tailport="read_1" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inAT3 -> MemoryControllerPro0 [headport="read_command_2" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inAT3" tailport="read_2" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inBT3 -> MemoryControllerPro0 [headport="read_command_3" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inBT3" tailport="read_3" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_oDataT1 -> MemoryControllerPro0 [headport="write_command_0" tailport="cgen_out_0" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_oDataT2 -> MemoryControllerPro0 [headport="write_command_1" tailport="cgen_out_0" label="{D{data:1}}"] Stream_34_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_a" tailport="output" label="{D{data:1}}"] Stream_29_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_b" tailport="output" label="{D{data:1}}"] Stream_39_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_c" tailport="output" label="{D{data:1}}"] Stream_28_pipeline_4 -> MemoryControllerInterface_b [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] Stream_33_pipeline_4 -> MemoryControllerInterface_a [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] Stream_38_pipeline_4 -> MemoryControllerInterface_c [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] }