Domů Procházet Nápověda
Přihlásit se
krailis
/
zynq-axi-tutorial
Sledovat 1
Oblíbit 0
Rozštěpit 0
Soubory Úkoly 0 Pull Requesty 0 Wiki
Větev: master
Větve Značky
zynq-axi-tut...
/
zedboard_axi4stream
/
create_add_one_axi4stream.tcl

create_add_one_axi4stream.tcl 3.2 KB
Trvalý odkaz Historie Surový

12345678910111213141516171819202122232425262728293031323334353637383940414243444546 
  1. start_gui
    2. 

  2. create_project add_one_zed_axi4stream ./add_one_zed_axi4stream -part xc7z020clg484-1
    3. 

  3. set_property board_part em.avnet.com:zed:part0:1.2 [current_project]
    4. 

  4. create_bd_design "system"
    5. 

  5. set_property ip_repo_paths  ../hls/add_one.prj/AXI4-Stream [current_project]
    6. 

  6. update_ip_catalog
    7. 

  7. startgroup
    8. 

  8. create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
    9. 

  9. endgroup
    10. 

  10. startgroup
    11. 

  11. set_property -dict [list CONFIG.preset {ZedBoard}] [get_bd_cells processing_system7_0]
    12. 

  12. set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0}] [get_bd_cells processing_system7_0]
    13. 

  13. set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] [get_bd_cells processing_system7_0]
    14. 

  14. endgroup
    15. 

  15. apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "0" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
    16. 

  16. startgroup
    17. 

  17. create_bd_cell -type ip -vlnv xilinx.com:hls:add_one:1.0 add_one_0
    18. 

  18. endgroup
    19. 

  19. startgroup
    20. 

  20. create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0
    21. 

  21. endgroup
    22. 

  22. startgroup
    23. 

  23. set_property -dict [list CONFIG.c_include_sg {0} CONFIG.c_sg_length_width {23} CONFIG.c_sg_include_stscntrl_strm {0}] [get_bd_cells axi_dma_0]
    24. 

  24. endgroup
    25. 

  25. apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" }  [get_bd_intf_pins axi_dma_0/S_AXI_LITE]
    26. 

  26. apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/axi_dma_0/M_AXI_MM2S" Clk "Auto" }  [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
    27. 

  27. apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Slave "/processing_system7_0/S_AXI_HP0" Clk "Auto" }  [get_bd_intf_pins axi_dma_0/M_AXI_S2MM]
    28. 

  28. regenerate_bd_layout
    29. 

  29. startgroup
    30. 

  30. create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0
    31. 

  31. endgroup
    32. 

  32. connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
    33. 

  33. connect_bd_net [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
    34. 

  34. connect_bd_net [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1]
    35. 

  35. connect_bd_intf_net [get_bd_intf_pins add_one_0/b] [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM]
    36. 

  36. connect_bd_intf_net [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins add_one_0/a]
    37. 

  37. connect_bd_net -net [get_bd_nets processing_system7_0_FCLK_CLK0] [get_bd_pins add_one_0/ap_clk] [get_bd_pins processing_system7_0/FCLK_CLK0]
    38. 

  38. connect_bd_net -net [get_bd_nets rst_processing_system7_0_102M_peripheral_aresetn] [get_bd_pins add_one_0/ap_rst_n] [get_bd_pins rst_processing_system7_0_102M/peripheral_aresetn]
    39. 

  39. save_bd_design 
    40. 

  40. validate_bd_design
    41. 

  41. make_wrapper -files [get_files /home/krailis/Downloads/zynq-axi-tutorial-master/zedboard_axi4stream/add_one_zed_axi4stream/add_one_zed_axi4stream.srcs/sources_1/bd/system/system.bd] -top
    42. 

  42. add_files -norecurse /home/krailis/Downloads/zynq-axi-tutorial-master/zedboard_axi4stream/add_one_zed_axi4stream/add_one_zed_axi4stream.srcs/sources_1/bd/system/hdl/system_wrapper.v
    43. 

  43. update_compile_order -fileset sources_1
    44. 

  44. update_compile_order -fileset sim_1
    45. 

  45. generate_target all [get_files  /home/krailis/Downloads/zynq-axi-tutorial-master/zedboard_axi4stream/add_one_zed_axi4stream/add_one_zed_axi4stream.srcs/sources_1/bd/system/system.bd]
    46. 

  46.