Home Explore Help
Sign In
exa2pro
/
starpu-max
Watch 19
Star 0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: f1946ab339
Branches Tags
starpu-max
/
tests
/
StreamFMA_MAX5C_DFE_SIM
/
scratch
/
Manager_StreamFMA_pullpush.dot

Manager_StreamFMA_pullpush.dot 5.8 KB
History Raw

123456789101112131415161718 
  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    4. 

  4. b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    5. 

  5. output[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : output</TD></TR></TABLE>>];
    6. 

  6. Stream_1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    7. 

  7. Stream_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    8. 

  8. Stream_8[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_8</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    9. 

  9. Stream_21[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_21</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    10. 

  10. a -> Stream_1 [headport="input" tailport="a" label="{D{data:1}}"]
    11. 

  11. b -> Stream_4 [headport="input" tailport="b" label="{D{data:1}}"]
    12. 

  12. StreamFMAKernel -> Stream_8 [headport="input" tailport="output" label="{D{data:1}}"]
    13. 

  13. Stream_1 -> StreamFMAKernel [headport="a" tailport="output" label="{D{data:1}}"]
    14. 

  14. Stream_4 -> StreamFMAKernel [headport="b" tailport="output" label="{D{data:1}}"]
    15. 

  15. Stream_8 -> Stream_21 [headport="input" tailport="output" label="{D{data:1}}"]
    16. 

  16. Stream_21 -> output [headport="output" tailport="output" label="{D{data:1}}"]
    17. 

  17. }
    18. 

  18.