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StreamFMA_MAX5C_DFE_SIM
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Manager_StreamFMA_final.dot

Manager_StreamFMA_final.dot 8.0 KB
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  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="a" ROWSPAN="1" COLSPAN="1">a<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    4. 

  4. b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="b" ROWSPAN="1" COLSPAN="1">b<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    5. 

  5. output[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : output</TD></TR></TABLE>>];
    6. 

  6. Stream_1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    7. 

  7. Stream_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    8. 

  8. Stream_8[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_8</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    9. 

  9. Stream_21[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_21</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    10. 

  10. Stream_11[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_11<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    11. 

  11. Stream_15[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_15<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    12. 

  12. Stream_13[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_13<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    13. 

  13. Stream_17[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_17<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    14. 

  14. Stream_19[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_19<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    15. 

  15. a -> Stream_11 [headport="input" tailport="a" label="{D{data:1}}"]
    16. 

  16. b -> Stream_15 [headport="input" tailport="b" label="{D{data:1}}"]
    17. 

  17. StreamFMAKernel -> Stream_19 [headport="input" tailport="output" label="{D{data:1}}"]
    18. 

  18. Stream_1 -> Stream_13 [headport="input" tailport="output" label="{D{data:1}}"]
    19. 

  19. Stream_4 -> Stream_17 [headport="input" tailport="output" label="{D{data:1}}"]
    20. 

  20. Stream_8 -> Stream_21 [headport="input" tailport="output" label="{D{data:1}}"]
    21. 

  21. Stream_21 -> output [headport="output" tailport="output" label="{D{data:1}}"]
    22. 

  22. Stream_11 -> Stream_1 [headport="input" tailport="output" label="{D{data:1}}"]
    23. 

  23. Stream_15 -> Stream_4 [headport="input" tailport="output" label="{D{data:1}}"]
    24. 

  24. Stream_13 -> StreamFMAKernel [headport="a" tailport="output" label="{D{data:1}}"]
    25. 

  25. Stream_17 -> StreamFMAKernel [headport="b" tailport="output" label="{D{data:1}}"]
    26. 

  26. Stream_19 -> Stream_8 [headport="input" tailport="output" label="{D{data:1}}"]
    27. 

  27. }
    28. 

  28.