starpu_slu_lu_model_21.sirocco 5.5 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. 0e8bce2b 16588800 0.000000e+00 8.483517e+04 1.709999e+04 1.781539e+06 1.572777e+11 21
  39. d39bff17 3276800 0.000000e+00 8.986208e+03 1.629610e+03 1.797242e+05 1.668151e+09 20
  40. 2c1922b7 819200 0.000000e+00 3.523655e+03 5.077738e+02 5.990214e+04 2.154576e+08 17
  41. ff82dda0 7372800 0.000000e+00 1.583302e+04 2.624137e+03 3.974089e+06 6.465024e+10 251
  42. ####################
  43. # COMB_1
  44. # number of types devices
  45. 1
  46. ####################
  47. # DEV_0
  48. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  49. 1
  50. ####################
  51. # DEV_0
  52. # device id
  53. 0
  54. ####################
  55. # DEV_0
  56. # number of cores
  57. 1
  58. ##########
  59. # number of implementations
  60. 1
  61. #####
  62. # Model for cuda0_impl0 (Comb1)
  63. # number of entries
  64. 4
  65. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  66. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  67. # a b c
  68. nan nan nan
  69. # not multiple-regression-base
  70. 0
  71. # hash size flops mean (us) dev (us) sum sum2 n
  72. 0e8bce2b 16588800 0.000000e+00 4.641113e+03 5.516013e+02 1.257742e+06 5.919777e+09 271
  73. d39bff17 3276800 0.000000e+00 8.365056e+02 1.344660e+02 1.396964e+05 1.198764e+08 167
  74. 2c1922b7 819200 0.000000e+00 2.882912e+02 5.271451e+01 7.409085e+04 2.207390e+07 257
  75. ff82dda0 7372800 0.000000e+00 1.570696e+03 2.281691e+02 4.115224e+05 6.600167e+08 262
  76. ####################
  77. # COMB_0
  78. # number of types devices
  79. 1
  80. ####################
  81. # DEV_0
  82. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  83. 1
  84. ####################
  85. # DEV_0
  86. # device id
  87. 2
  88. ####################
  89. # DEV_0
  90. # number of cores
  91. 1
  92. ##########
  93. # number of implementations
  94. 1
  95. #####
  96. # Model for cuda2_impl0 (Comb0)
  97. # number of entries
  98. 4
  99. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  100. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  101. # a b c
  102. nan nan nan
  103. # not multiple-regression-base
  104. 0
  105. # hash size flops mean (us) dev (us) sum sum2 n
  106. 0e8bce2b 16588800 0.000000e+00 4.556926e+03 5.099622e+02 1.048093e+06 4.835897e+09 230
  107. d39bff17 3276800 0.000000e+00 7.019049e+02 1.632697e+02 1.109010e+05 8.205375e+07 158
  108. 2c1922b7 819200 0.000000e+00 9.967334e+01 2.197557e+01 2.372225e+04 2.479413e+06 238
  109. ff82dda0 7372800 0.000000e+00 1.571709e+03 2.150516e+02 4.007858e+05 6.417117e+08 255
  110. ####################
  111. # COMB_3
  112. # number of types devices
  113. 1
  114. ####################
  115. # DEV_0
  116. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  117. 1
  118. ####################
  119. # DEV_0
  120. # device id
  121. 3
  122. ####################
  123. # DEV_0
  124. # number of cores
  125. 1
  126. ##########
  127. # number of implementations
  128. 1
  129. #####
  130. # Model for cuda3_impl0 (Comb3)
  131. # number of entries
  132. 4
  133. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  134. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  135. # a b c
  136. nan nan nan
  137. # not multiple-regression-base
  138. 0
  139. # hash size flops mean (us) dev (us) sum sum2 n
  140. 0e8bce2b 16588800 0.000000e+00 4.650733e+03 7.073225e+02 1.232444e+06 5.864350e+09 265
  141. d39bff17 3276800 0.000000e+00 8.352707e+02 1.515223e+02 1.587014e+05 1.369209e+08 190
  142. 2c1922b7 819200 0.000000e+00 2.858293e+02 5.241353e+01 7.460146e+04 2.204030e+07 261
  143. ff82dda0 7372800 0.000000e+00 1.569547e+03 2.419662e+02 2.589752e+05 4.161341e+08 165
  144. ####################
  145. # COMB_2
  146. # number of types devices
  147. 1
  148. ####################
  149. # DEV_0
  150. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  151. 1
  152. ####################
  153. # DEV_0
  154. # device id
  155. 1
  156. ####################
  157. # DEV_0
  158. # number of cores
  159. 1
  160. ##########
  161. # number of implementations
  162. 1
  163. #####
  164. # Model for cuda1_impl0 (Comb2)
  165. # number of entries
  166. 4
  167. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  168. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  169. # a b c
  170. nan nan nan
  171. # not multiple-regression-base
  172. 0
  173. # hash size flops mean (us) dev (us) sum sum2 n
  174. 0e8bce2b 16588800 0.000000e+00 4.671203e+03 5.859459e+02 1.331293e+06 6.316588e+09 285
  175. d39bff17 3276800 0.000000e+00 8.453596e+02 1.395049e+02 1.420204e+05 1.233279e+08 168
  176. 2c1922b7 819200 0.000000e+00 2.930233e+02 5.590601e+01 5.362326e+04 1.628483e+07 183
  177. ff82dda0 7372800 0.000000e+00 1.591448e+03 2.256700e+02 2.387172e+05 3.875451e+08 150