overlap_sleep_1024_24.mirage 3.2 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 4
  8. ####################
  9. # COMB_1
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, MPI_MS - 5)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb1)
  29. # number of entries
  30. 1
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. a3d3725e 1024 0.000000e+00 8.457435e+01 8.456846e+01 6.080896e+05 5.145841e+07 7190
  39. ####################
  40. # COMB_0
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, MPI_MS - 5)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 0
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda0_impl0 (Comb0)
  60. # number of entries
  61. 1
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # not multiple-regression-base
  67. 0
  68. # hash size flops mean (us) dev (us) sum sum2 n
  69. a3d3725e 1024 0.000000e+00 8.959785e+01 8.957735e+01 1.959505e+05 1.756781e+07 2187
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, MPI_MS - 5)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 2
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda2_impl0 (Comb2)
  91. # number of entries
  92. 1
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # not multiple-regression-base
  98. 0
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. a3d3725e 1024 0.000000e+00 9.097446e+01 8.933429e+01 2.547285e+03 2.318591e+05 28
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, MPI_MS - 5)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 1
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda1_impl0 (Comb3)
  122. # number of entries
  123. 1
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # not multiple-regression-base
  129. 0
  130. # hash size flops mean (us) dev (us) sum sum2 n
  131. a3d3725e 1024 0.000000e+00 9.082936e+01 9.075245e+01 5.368015e+04 4.878224e+06 591