cl_update.sirocco 5.0 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_1
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 3
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda3_impl0 (Comb1)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. 8ec75d42 14753312 0.000000e+00 1.292737e+03 8.111826e+01 1.783977e+06 2.315293e+09 1380
  39. 6d78e48f 4461600 0.000000e+00 7.254397e+02 8.693801e+01 2.717497e+06 1.999693e+09 3746
  40. 49ec0825 34613280 0.000000e+00 2.847204e+03 1.159244e+02 5.255939e+06 1.498954e+10 1846
  41. ####################
  42. # COMB_0
  43. # number of types devices
  44. 1
  45. ####################
  46. # DEV_0
  47. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  48. 0
  49. ####################
  50. # DEV_0
  51. # device id
  52. 0
  53. ####################
  54. # DEV_0
  55. # number of cores
  56. 1
  57. ##########
  58. # number of implementations
  59. 1
  60. #####
  61. # Model for cpu0_impl0 (Comb0)
  62. # number of entries
  63. 3
  64. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  65. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  66. # a b c
  67. nan nan nan
  68. # not multiple-regression-base
  69. 0
  70. # hash size flops mean (us) dev (us) sum sum2 n
  71. 8ec75d42 14753312 0.000000e+00 2.010356e+04 1.739800e+03 4.201644e+06 8.510064e+10 209
  72. 6d78e48f 4461600 0.000000e+00 6.471465e+03 9.708551e+02 2.344612e+07 1.551456e+11 3623
  73. 49ec0825 34613280 0.000000e+00 4.705100e+04 5.067137e+03 1.383299e+07 6.584049e+11 294
  74. ####################
  75. # COMB_3
  76. # number of types devices
  77. 1
  78. ####################
  79. # DEV_0
  80. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  81. 1
  82. ####################
  83. # DEV_0
  84. # device id
  85. 1
  86. ####################
  87. # DEV_0
  88. # number of cores
  89. 1
  90. ##########
  91. # number of implementations
  92. 1
  93. #####
  94. # Model for cuda1_impl0 (Comb3)
  95. # number of entries
  96. 3
  97. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  98. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  99. # a b c
  100. nan nan nan
  101. # not multiple-regression-base
  102. 0
  103. # hash size flops mean (us) dev (us) sum sum2 n
  104. 8ec75d42 14753312 0.000000e+00 1.333639e+03 8.095890e+01 1.871095e+06 2.504561e+09 1403
  105. 6d78e48f 4461600 0.000000e+00 7.466797e+02 9.599725e+01 2.594712e+06 1.969443e+09 3475
  106. 49ec0825 34613280 0.000000e+00 2.914989e+03 1.085303e+02 5.037101e+06 1.470345e+10 1728
  107. ####################
  108. # COMB_4
  109. # number of types devices
  110. 1
  111. ####################
  112. # DEV_0
  113. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  114. 1
  115. ####################
  116. # DEV_0
  117. # device id
  118. 0
  119. ####################
  120. # DEV_0
  121. # number of cores
  122. 1
  123. ##########
  124. # number of implementations
  125. 1
  126. #####
  127. # Model for cuda0_impl0 (Comb4)
  128. # number of entries
  129. 3
  130. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  131. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  132. # a b c
  133. nan nan nan
  134. # not multiple-regression-base
  135. 0
  136. # hash size flops mean (us) dev (us) sum sum2 n
  137. 8ec75d42 14753312 0.000000e+00 1.319437e+03 8.470023e+01 1.921100e+06 2.545216e+09 1456
  138. 6d78e48f 4461600 0.000000e+00 7.342135e+02 9.435309e+01 2.608661e+06 1.946944e+09 3553
  139. 49ec0825 34613280 0.000000e+00 2.843027e+03 1.019747e+02 5.080489e+06 1.446255e+10 1787
  140. ####################
  141. # COMB_2
  142. # number of types devices
  143. 1
  144. ####################
  145. # DEV_0
  146. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  147. 1
  148. ####################
  149. # DEV_0
  150. # device id
  151. 2
  152. ####################
  153. # DEV_0
  154. # number of cores
  155. 1
  156. ##########
  157. # number of implementations
  158. 1
  159. #####
  160. # Model for cuda2_impl0 (Comb2)
  161. # number of entries
  162. 3
  163. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  164. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  165. # a b c
  166. nan nan nan
  167. # not multiple-regression-base
  168. 0
  169. # hash size flops mean (us) dev (us) sum sum2 n
  170. 8ec75d42 14753312 0.000000e+00 1.324805e+03 7.460278e+01 1.748742e+06 2.324088e+09 1320
  171. 6d78e48f 4461600 0.000000e+00 7.321696e+02 8.668478e+01 2.571380e+06 1.909076e+09 3512
  172. 49ec0825 34613280 0.000000e+00 2.873920e+03 1.173279e+02 5.566783e+06 1.602515e+10 1937