starpu-max/tests/StreamFMA_MAX5C_DFE_SIM/scratch/Manager_StreamFMA_Final.mxg

<?xml version="1.0" encoding="UTF-8" ?>
<ManagerGraph version="2018.3.1" design_name="Manager_StreamFMA" compilation_phase="Final" hardwareBuild="false">
	<Node id="5" instanceName="b" type="Input">
		<Output clock="PCIE" name="b" type="PUSH 2" width="128">
			<Stream name="Stream_6" sink="30" />
		</Output>
	</Node>
	<Node id="2" instanceName="a" type="Input">
		<Output clock="PCIE" name="a" type="PUSH 2" width="128">
			<Stream name="Stream_3" sink="26" />
		</Output>
	</Node>
	<Node id="30" instanceName="Stream_15" type="Fifo">
		<Input clock="PCIE" name="input" type="PUSH 2" width="128">
			<Stream name="Stream_31" source="5" />
		</Input>
		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
			<Stream name="Stream_32" sink="14" />
		</Output>
	</Node>
	<Node id="26" instanceName="Stream_11" type="Fifo">
		<Input clock="PCIE" name="input" type="PUSH 2" width="128">
			<Stream name="Stream_27" source="2" />
		</Input>
		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
			<Stream name="Stream_28" sink="10" />
		</Output>
	</Node>
	<Node id="10" instanceName="Stream_1" type="DualAspectMux">
		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
			<Stream name="Stream_29" source="26" />
		</Input>
		<Output clock="PCIE" name="output" type="PUSH 2" width="32">
			<Stream name="Stream_12" sink="34" />
		</Output>
	</Node>
	<Node id="14" instanceName="Stream_4" type="DualAspectMux">
		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
			<Stream name="Stream_33" source="30" />
		</Input>
		<Output clock="PCIE" name="output" type="PUSH 2" width="32">
			<Stream name="Stream_16" sink="38" />
		</Output>
	</Node>
	<Node id="38" instanceName="Stream_17" type="Fifo">
		<Input clock="PCIE" name="input" type="PUSH 2" width="32">
			<Stream name="Stream_39" source="14" />
		</Input>
		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
			<Stream name="Stream_40" sink="0" />
		</Output>
	</Node>
	<Node id="34" instanceName="Stream_13" type="Fifo">
		<Input clock="PCIE" name="input" type="PUSH 2" width="32">
			<Stream name="Stream_35" source="10" />
		</Input>
		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
			<Stream name="Stream_36" sink="0" />
		</Output>
	</Node>
	<Node id="0" instanceName="StreamFMAKernel" type="Kernel">
		<PxgFile phase="original">StreamFMA-StreamFMAKernel-original.pxg</PxgFile>
		<PxgFile phase="final-simulation">StreamFMA-StreamFMAKernel-final-simulation.pxg</PxgFile>
		<Input clock="STREAM" name="a" type="PULL el=1 ael=2" width="32">
			<Stream name="Stream_37" source="34" />
		</Input>
		<Input clock="STREAM" name="b" type="PULL el=1 ael=2" width="32">
			<Stream name="Stream_41" source="38" />
		</Input>
		<Output clock="STREAM" name="output" type="PUSH 5" width="32">
			<Stream name="Stream_9" sink="42" />
		</Output>
	</Node>
	<Node id="42" instanceName="Stream_19" type="Fifo">
		<Input clock="STREAM" name="input" type="PUSH 5" width="32">
			<Stream name="Stream_43" source="0" />
		</Input>
		<Output clock="PCIE" name="output" type="PULL el=1" width="32">
			<Stream name="Stream_44" sink="18" />
		</Output>
	</Node>
	<Node id="18" instanceName="Stream_8" type="DualAspectReg">
		<Input clock="PCIE" name="input" type="PULL el=1" width="32">
			<Stream name="Stream_45" source="42" />
		</Input>
		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
			<Stream name="Stream_20" sink="22" />
		</Output>
	</Node>
	<Node id="22" instanceName="Stream_21" type="PullPushAdapter">
		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
			<Stream name="Stream_23" source="18" />
		</Input>
		<Output clock="PCIE" name="output" type="PUSH 1" width="128">
			<Stream name="Stream_24" sink="7" />
		</Output>
	</Node>
	<Node id="7" instanceName="output" type="Output">
		<Input clock="PCIE" name="output" type="PUSH 1" width="128">
			<Stream name="Stream_25" source="22" />
		</Input>
	</Node>
</ManagerGraph>