save_cl_bottom.sirocco 5.0 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. 4af260f6 14678040 0.000000e+00 3.447447e+01 7.398265e+00 3.237153e+04 1.167387e+06 939
  39. fb4b8624 4427800 0.000000e+00 5.439097e+01 1.253425e+01 3.094846e+05 1.772711e+07 5690
  40. f2ff9ae5 34480152 0.000000e+00 5.041329e+01 1.085485e+01 6.226042e+04 3.284270e+06 1235
  41. ####################
  42. # COMB_1
  43. # number of types devices
  44. 1
  45. ####################
  46. # DEV_0
  47. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  48. 1
  49. ####################
  50. # DEV_0
  51. # device id
  52. 3
  53. ####################
  54. # DEV_0
  55. # number of cores
  56. 1
  57. ##########
  58. # number of implementations
  59. 1
  60. #####
  61. # Model for cuda3_impl0 (Comb1)
  62. # number of entries
  63. 3
  64. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  65. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  66. # a b c
  67. nan nan nan
  68. # not multiple-regression-base
  69. 0
  70. # hash size flops mean (us) dev (us) sum sum2 n
  71. 4af260f6 14678040 0.000000e+00 3.176283e+01 6.812714e+00 1.673901e+04 5.561382e+05 527
  72. fb4b8624 4427800 0.000000e+00 5.311651e+01 1.346481e+01 1.290731e+04 7.296474e+05 243
  73. f2ff9ae5 34480152 0.000000e+00 4.192896e+01 9.759572e+00 3.207566e+04 1.417765e+06 765
  74. ####################
  75. # COMB_2
  76. # number of types devices
  77. 1
  78. ####################
  79. # DEV_0
  80. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  81. 1
  82. ####################
  83. # DEV_0
  84. # device id
  85. 2
  86. ####################
  87. # DEV_0
  88. # number of cores
  89. 1
  90. ##########
  91. # number of implementations
  92. 1
  93. #####
  94. # Model for cuda2_impl0 (Comb2)
  95. # number of entries
  96. 3
  97. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  98. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  99. # a b c
  100. nan nan nan
  101. # not multiple-regression-base
  102. 0
  103. # hash size flops mean (us) dev (us) sum sum2 n
  104. 4af260f6 14678040 0.000000e+00 3.786531e+01 9.328071e+00 1.991715e+04 7.999380e+05 526
  105. fb4b8624 4427800 0.000000e+00 5.555598e+01 1.303330e+01 9.444517e+03 5.535768e+05 170
  106. f2ff9ae5 34480152 0.000000e+00 4.359390e+01 1.022197e+01 2.218929e+04 1.020503e+06 509
  107. ####################
  108. # COMB_3
  109. # number of types devices
  110. 1
  111. ####################
  112. # DEV_0
  113. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  114. 1
  115. ####################
  116. # DEV_0
  117. # device id
  118. 1
  119. ####################
  120. # DEV_0
  121. # number of cores
  122. 1
  123. ##########
  124. # number of implementations
  125. 1
  126. #####
  127. # Model for cuda1_impl0 (Comb3)
  128. # number of entries
  129. 3
  130. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  131. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  132. # a b c
  133. nan nan nan
  134. # not multiple-regression-base
  135. 0
  136. # hash size flops mean (us) dev (us) sum sum2 n
  137. 4af260f6 14678040 0.000000e+00 4.035980e+01 9.947105e+00 1.989738e+04 8.518341e+05 493
  138. fb4b8624 4427800 0.000000e+00 8.863692e+01 1.909792e+01 1.161144e+04 1.076982e+06 131
  139. f2ff9ae5 34480152 0.000000e+00 3.838146e+01 9.359960e+00 2.890124e+04 1.175241e+06 753
  140. ####################
  141. # COMB_4
  142. # number of types devices
  143. 1
  144. ####################
  145. # DEV_0
  146. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  147. 1
  148. ####################
  149. # DEV_0
  150. # device id
  151. 0
  152. ####################
  153. # DEV_0
  154. # number of cores
  155. 1
  156. ##########
  157. # number of implementations
  158. 1
  159. #####
  160. # Model for cuda0_impl0 (Comb4)
  161. # number of entries
  162. 3
  163. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  164. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  165. # a b c
  166. nan nan nan
  167. # not multiple-regression-base
  168. 0
  169. # hash size flops mean (us) dev (us) sum sum2 n
  170. 4af260f6 14678040 0.000000e+00 3.505264e+01 8.845541e+00 1.945422e+04 7.253469e+05 555
  171. fb4b8624 4427800 0.000000e+00 4.717545e+01 1.027132e+01 6.227160e+03 3.076951e+05 132
  172. f2ff9ae5 34480152 0.000000e+00 3.110432e+01 6.170515e+00 2.370149e+04 7.662320e+05 762