starpu_slu_lu_model_21.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 0e8bce2b 16588800 0.000000e+00 8.483517e+04 1.709999e+04 1.781539e+06 1.572777e+11 21
  37. d39bff17 3276800 0.000000e+00 8.986208e+03 1.629610e+03 1.797242e+05 1.668151e+09 20
  38. 2c1922b7 819200 0.000000e+00 3.523655e+03 5.077738e+02 5.990214e+04 2.154576e+08 17
  39. ff82dda0 7372800 0.000000e+00 1.583302e+04 2.624137e+03 3.974089e+06 6.465024e+10 251
  40. ####################
  41. # COMB_1
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 0
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda0_impl0 (Comb1)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 0e8bce2b 16588800 0.000000e+00 4.641113e+03 5.516013e+02 1.257742e+06 5.919777e+09 271
  69. d39bff17 3276800 0.000000e+00 8.365056e+02 1.344660e+02 1.396964e+05 1.198764e+08 167
  70. 2c1922b7 819200 0.000000e+00 2.882912e+02 5.271451e+01 7.409085e+04 2.207390e+07 257
  71. ff82dda0 7372800 0.000000e+00 1.570696e+03 2.281691e+02 4.115224e+05 6.600167e+08 262
  72. ####################
  73. # COMB_0
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 2
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda2_impl0 (Comb0)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 0e8bce2b 16588800 0.000000e+00 4.556926e+03 5.099622e+02 1.048093e+06 4.835897e+09 230
  101. d39bff17 3276800 0.000000e+00 7.019049e+02 1.632697e+02 1.109010e+05 8.205375e+07 158
  102. 2c1922b7 819200 0.000000e+00 9.967334e+01 2.197557e+01 2.372225e+04 2.479413e+06 238
  103. ff82dda0 7372800 0.000000e+00 1.571709e+03 2.150516e+02 4.007858e+05 6.417117e+08 255
  104. ####################
  105. # COMB_3
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 3
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda3_impl0 (Comb3)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 0e8bce2b 16588800 0.000000e+00 4.650733e+03 7.073225e+02 1.232444e+06 5.864350e+09 265
  133. d39bff17 3276800 0.000000e+00 8.352707e+02 1.515223e+02 1.587014e+05 1.369209e+08 190
  134. 2c1922b7 819200 0.000000e+00 2.858293e+02 5.241353e+01 7.460146e+04 2.204030e+07 261
  135. ff82dda0 7372800 0.000000e+00 1.569547e+03 2.419662e+02 2.589752e+05 4.161341e+08 165
  136. ####################
  137. # COMB_2
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 1
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda1_impl0 (Comb2)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 0e8bce2b 16588800 0.000000e+00 4.671203e+03 5.859459e+02 1.331293e+06 6.316588e+09 285
  165. d39bff17 3276800 0.000000e+00 8.453596e+02 1.395049e+02 1.420204e+05 1.233279e+08 168
  166. 2c1922b7 819200 0.000000e+00 2.930233e+02 5.590601e+01 5.362326e+04 1.628483e+07 183
  167. ff82dda0 7372800 0.000000e+00 1.591448e+03 2.256700e+02 2.387172e+05 3.875451e+08 150