starpu_slu_lu_model_12.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 0e8bce2b 16588800 0.000000e+00 5.637990e+04 1.036285e+04 8.118706e+06 4.731958e+11 144
  37. d39bff17 3276800 0.000000e+00 5.106660e+03 6.848530e+02 2.134584e+06 1.109665e+10 418
  38. 2c1922b7 819200 0.000000e+00 4.245334e+03 7.020174e+02 6.368000e+04 2.777353e+08 15
  39. ff82dda0 7372800 0.000000e+00 1.726784e+04 3.264426e+03 3.021872e+06 5.404608e+10 175
  40. ####################
  41. # COMB_3
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 3
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda3_impl0 (Comb3)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 0e8bce2b 16588800 0.000000e+00 5.668892e+03 6.964909e+02 1.394547e+06 8.024874e+09 246
  69. d39bff17 3276800 0.000000e+00 1.216432e+03 1.410794e+02 1.934127e+05 2.384382e+08 159
  70. 2c1922b7 819200 0.000000e+00 4.901281e+02 6.729653e+01 6.616730e+04 3.304185e+07 135
  71. ff82dda0 7372800 0.000000e+00 2.106719e+03 2.638200e+02 5.646006e+05 1.208108e+09 268
  72. ####################
  73. # COMB_2
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 1
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda1_impl0 (Comb2)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 0e8bce2b 16588800 0.000000e+00 5.677828e+03 6.218985e+02 1.311578e+06 7.536257e+09 231
  101. d39bff17 3276800 0.000000e+00 1.199302e+03 1.658297e+02 1.774966e+05 2.169419e+08 148
  102. 2c1922b7 819200 0.000000e+00 4.968224e+02 7.860110e+01 5.415364e+04 2.757816e+07 109
  103. ff82dda0 7372800 0.000000e+00 2.138085e+03 2.696288e+02 6.371492e+05 1.383944e+09 298
  104. ####################
  105. # COMB_0
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 2
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda2_impl0 (Comb0)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 0e8bce2b 16588800 0.000000e+00 5.593766e+03 7.653530e+02 1.510317e+06 8.606516e+09 270
  133. d39bff17 3276800 0.000000e+00 1.148300e+03 2.163448e+02 2.021009e+05 2.403102e+08 176
  134. 2c1922b7 819200 0.000000e+00 8.901347e+01 1.918734e+01 2.412265e+04 2.247011e+06 271
  135. ff82dda0 7372800 0.000000e+00 2.196957e+03 3.265420e+02 4.349975e+05 9.767837e+08 198
  136. ####################
  137. # COMB_1
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 0
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda0_impl0 (Comb1)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 0e8bce2b 16588800 0.000000e+00 5.652338e+03 6.245997e+02 1.520479e+06 8.699205e+09 269
  165. d39bff17 3276800 0.000000e+00 1.203544e+03 1.679024e+02 2.286733e+05 2.805746e+08 190
  166. 2c1922b7 819200 0.000000e+00 4.930666e+02 7.623523e+01 7.642532e+04 3.858360e+07 155
  167. ff82dda0 7372800 0.000000e+00 2.164310e+03 2.607466e+02 4.869698e+05 1.069251e+09 225