starpu_sgemm_gemm.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_2
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb2)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 492beed5 33177600 7.077888e+09 2.745578e+03 3.064191e+02 6.616844e+05 1.839335e+09 241
  37. 0b0b0ce8 3686400 2.621440e+08 1.582927e+02 3.333442e+01 3.434951e+04 5.678402e+06 217
  38. 4220e23d 14745600 2.097152e+09 8.206871e+02 1.017181e+02 1.148962e+05 9.574235e+07 140
  39. 87a7dc42 74649600 2.388787e+10 9.813897e+03 7.998509e+02 1.570224e+06 1.551237e+10 160
  40. ####################
  41. # COMB_1
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 3
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda3_impl0 (Comb1)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 492beed5 33177600 7.077888e+09 2.686428e+03 2.002215e+02 6.716071e+05 1.814247e+09 250
  69. 0b0b0ce8 3686400 2.621440e+08 1.630480e+02 3.438768e+01 3.097912e+04 5.275762e+06 190
  70. 4220e23d 14745600 2.097152e+09 8.448030e+02 7.773742e+01 2.433033e+05 2.072837e+08 288
  71. 87a7dc42 74649600 2.388787e+10 9.873153e+03 8.026227e+02 1.579704e+06 1.569974e+10 160
  72. ####################
  73. # COMB_0
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 1
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda1_impl0 (Comb0)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 492beed5 33177600 7.077888e+09 2.791098e+03 3.147711e+02 6.503258e+05 1.838209e+09 233
  101. 0b0b0ce8 3686400 2.621440e+08 1.624855e+02 3.298013e+01 2.940987e+04 4.975550e+06 181
  102. 4220e23d 14745600 2.097152e+09 8.152506e+02 1.017614e+02 1.173961e+05 9.719839e+07 144
  103. 87a7dc42 74649600 2.388787e+10 1.001360e+04 7.827579e+02 1.582149e+06 1.593981e+10 158
  104. ####################
  105. # COMB_3
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 2
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda2_impl0 (Comb3)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 492beed5 33177600 7.077888e+09 2.754203e+03 2.682327e+02 6.830422e+05 1.899080e+09 248
  133. 0b0b0ce8 3686400 2.621440e+08 1.622246e+02 3.553894e+01 3.714942e+04 6.315779e+06 229
  134. 4220e23d 14745600 2.097152e+09 8.611626e+02 9.290485e+01 2.411255e+05 2.100651e+08 280
  135. 87a7dc42 74649600 2.388787e+10 9.935915e+03 7.366769e+02 1.569875e+06 1.568389e+10 158
  136. ####################
  137. # COMB_4
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 0
  144. ####################
  145. # DEV_0
  146. # device id
  147. 0
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cpu0_impl0 (Comb4)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 492beed5 33177600 7.077888e+09 1.712078e+05 4.163047e+04 2.773567e+07 5.029326e+12 162
  165. 0b0b0ce8 3686400 2.621440e+08 6.441655e+03 1.152866e+03 3.220827e+05 2.141201e+09 50
  166. 4220e23d 14745600 2.097152e+09 4.927734e+04 1.166029e+04 5.913281e+06 3.077063e+11 120
  167. 87a7dc42 74649600 2.388787e+10 5.091210e+05 1.022002e+05 6.974957e+07 3.694192e+13 137