starpu_dlu_lu_model_21.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 14745600 0.000000e+00 4.935132e+04 1.056942e+04 1.875350e+06 9.679609e+10 38
  37. 2c1922b7 1638400 0.000000e+00 1.386830e+03 2.636504e+02 1.256468e+06 1.805486e+09 906
  38. d39bff17 6553600 0.000000e+00 1.762919e+04 3.396463e+03 6.170218e+05 1.128135e+10 35
  39. 0e8bce2b 33177600 0.000000e+00 2.090375e+05 4.666688e+04 3.762675e+06 8.257406e+11 18
  40. ####################
  41. # COMB_0
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 2
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda2_impl0 (Comb0)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. ff82dda0 14745600 0.000000e+00 2.580226e+03 3.710017e+02 5.495882e+05 1.447380e+09 213
  69. 2c1922b7 1638400 0.000000e+00 3.441326e+02 6.695097e+01 4.267244e+04 1.524080e+07 124
  70. d39bff17 6553600 0.000000e+00 9.089165e+02 1.570596e+02 1.590604e+05 1.488895e+08 175
  71. 0e8bce2b 33177600 0.000000e+00 5.659456e+03 7.119452e+02 1.058318e+06 6.084289e+09 187
  72. ####################
  73. # COMB_2
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 0
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda0_impl0 (Comb2)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. ff82dda0 14745600 0.000000e+00 2.485190e+03 3.288259e+02 6.188122e+05 1.564789e+09 249
  101. 2c1922b7 1638400 0.000000e+00 3.565977e+02 7.541526e+01 3.672956e+04 1.368348e+07 103
  102. d39bff17 6553600 0.000000e+00 9.441529e+02 1.527244e+02 2.398148e+05 2.323464e+08 254
  103. 0e8bce2b 33177600 0.000000e+00 5.713813e+03 7.827526e+02 8.456444e+05 4.922534e+09 148
  104. ####################
  105. # COMB_3
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 3
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda3_impl0 (Comb3)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. ff82dda0 14745600 0.000000e+00 2.615067e+03 4.428563e+02 5.334737e+05 1.435078e+09 204
  133. 2c1922b7 1638400 0.000000e+00 3.667814e+02 6.561130e+01 3.227676e+04 1.221734e+07 88
  134. d39bff17 6553600 0.000000e+00 9.018562e+02 1.587421e+02 1.470026e+05 1.366826e+08 163
  135. 0e8bce2b 33177600 0.000000e+00 5.604694e+03 6.527594e+02 1.132148e+06 6.431415e+09 202
  136. ####################
  137. # COMB_1
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 1
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda1_impl0 (Comb1)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. ff82dda0 14745600 0.000000e+00 2.480709e+03 3.749281e+02 4.514890e+05 1.145597e+09 182
  165. 2c1922b7 1638400 0.000000e+00 3.718262e+02 7.249781e+01 2.342505e+04 9.041172e+06 63
  166. d39bff17 6553600 0.000000e+00 9.130900e+02 1.739240e+02 2.182285e+05 2.064919e+08 239
  167. 0e8bce2b 33177600 0.000000e+00 5.804941e+03 6.806052e+02 9.113758e+05 5.363209e+09 157