starpu_dlu_lu_model_12.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 14745600 0.000000e+00 3.402547e+04 6.005726e+03 7.111323e+06 2.495045e+11 209
  37. 2c1922b7 1638400 0.000000e+00 6.443940e+03 1.476966e+03 1.610985e+05 1.092645e+09 25
  38. d39bff17 6553600 0.000000e+00 1.041247e+04 1.992240e+03 3.092503e+06 3.337940e+10 297
  39. 0e8bce2b 33177600 0.000000e+00 1.103734e+05 1.699353e+04 1.037510e+07 1.172281e+12 94
  40. ####################
  41. # COMB_1
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 1
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda1_impl0 (Comb1)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. ff82dda0 14745600 0.000000e+00 3.238292e+03 4.902889e+02 6.768030e+05 2.241926e+09 209
  69. 2c1922b7 1638400 0.000000e+00 5.889641e+02 1.063542e+02 1.272162e+05 7.736903e+07 216
  70. d39bff17 6553600 0.000000e+00 1.349909e+03 1.936514e+02 2.942801e+05 4.054266e+08 218
  71. 0e8bce2b 33177600 0.000000e+00 7.038455e+03 8.353918e+02 1.182460e+06 8.439938e+09 168
  72. ####################
  73. # COMB_2
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 0
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda0_impl0 (Comb2)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. ff82dda0 14745600 0.000000e+00 3.179744e+03 4.016259e+02 6.804652e+05 2.198224e+09 214
  101. 2c1922b7 1638400 0.000000e+00 5.796961e+02 1.048897e+02 1.199971e+05 7.183924e+07 207
  102. d39bff17 6553600 0.000000e+00 1.343917e+03 2.039127e+02 2.244341e+05 3.085646e+08 167
  103. 0e8bce2b 33177600 0.000000e+00 6.913467e+03 8.366528e+02 1.244424e+06 8.729283e+09 180
  104. ####################
  105. # COMB_3
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 3
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda3_impl0 (Comb3)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. ff82dda0 14745600 0.000000e+00 3.362936e+03 5.457359e+02 6.524096e+05 2.251791e+09 194
  133. 2c1922b7 1638400 0.000000e+00 5.405600e+02 9.344101e+01 1.513568e+05 8.426217e+07 280
  134. d39bff17 6553600 0.000000e+00 1.275634e+03 1.830051e+02 2.270629e+05 2.956105e+08 178
  135. 0e8bce2b 33177600 0.000000e+00 6.852169e+03 8.897789e+02 8.291125e+05 5.777016e+09 121
  136. ####################
  137. # COMB_0
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 2
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda2_impl0 (Comb0)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. ff82dda0 14745600 0.000000e+00 3.306190e+03 4.921154e+02 7.009122e+05 2.368690e+09 212
  165. 2c1922b7 1638400 0.000000e+00 5.641572e+02 1.012475e+02 1.376544e+05 8.015997e+07 244
  166. d39bff17 6553600 0.000000e+00 1.355727e+03 1.656730e+02 2.331851e+05 3.208564e+08 172
  167. 0e8bce2b 33177600 0.000000e+00 6.732998e+03 6.928655e+02 1.144610e+06 7.788266e+09 170