starpu_dlu_lu_model_11.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 617e5fe6 7372800 0.000000e+00 1.778570e+05 1.735127e+04 1.778570e+06 3.193419e+11 10
  37. cea37d6d 819200 0.000000e+00 5.904224e+03 6.575598e+02 5.668055e+05 3.388055e+09 96
  38. afdd228b 3276800 0.000000e+00 4.953149e+04 6.709149e+03 6.439093e+05 3.247895e+10 13
  39. 25ebb669 16588800 0.000000e+00 7.801727e+05 1.214440e+05 7.801727e+06 6.234180e+12 10
  40. ####################
  41. # COMB_0
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 2
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda2_impl0 (Comb0)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 617e5fe6 7372800 0.000000e+00 5.552387e+04 5.714037e+03 1.054954e+06 5.919546e+10 19
  69. cea37d6d 819200 0.000000e+00 9.707597e+03 9.439210e+02 9.707597e+04 9.512842e+08 10
  70. afdd228b 3276800 0.000000e+00 2.633937e+04 3.608518e+03 3.950905e+05 1.060175e+10 15
  71. 25ebb669 16588800 0.000000e+00 1.397955e+05 9.676594e+03 1.537750e+06 2.160006e+11 11
  72. ####################
  73. # COMB_2
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 0
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda0_impl0 (Comb2)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 617e5fe6 7372800 0.000000e+00 5.675882e+04 6.232185e+03 1.248694e+06 7.172888e+10 22
  101. cea37d6d 819200 0.000000e+00 9.541018e+03 9.285702e+02 9.541018e+04 9.189326e+08 10
  102. afdd228b 3276800 0.000000e+00 2.651477e+04 2.554649e+03 3.181772e+05 8.514711e+09 12
  103. 25ebb669 16588800 0.000000e+00 1.382255e+05 7.304438e+03 1.382255e+06 1.915965e+11 10
  104. ####################
  105. # COMB_1
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 1
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda1_impl0 (Comb1)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 617e5fe6 7372800 0.000000e+00 5.624387e+04 5.549003e+03 8.436581e+05 4.791247e+10 15
  133. cea37d6d 819200 0.000000e+00 9.661577e+03 7.114114e+02 9.661577e+04 9.385217e+08 10
  134. afdd228b 3276800 0.000000e+00 2.574090e+04 2.071791e+03 5.148179e+05 1.333772e+10 20
  135. 25ebb669 16588800 0.000000e+00 1.361676e+05 1.958095e+03 1.770178e+06 2.410907e+11 13
  136. ####################
  137. # COMB_3
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 3
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda3_impl0 (Comb3)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 617e5fe6 7372800 0.000000e+00 5.895007e+04 8.369498e+03 7.663509e+05 4.608707e+10 13
  165. cea37d6d 819200 0.000000e+00 9.910778e+03 1.200981e+03 9.910778e+04 9.966588e+08 10
  166. afdd228b 3276800 0.000000e+00 2.572979e+04 2.095041e+03 5.917851e+05 1.532746e+10 23
  167. 25ebb669 16588800 0.000000e+00 1.422314e+05 1.728252e+04 1.422314e+06 2.052844e+11 10