starpu_dgemm_gemm.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_2
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb2)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 492beed5 66355200 7.077888e+09 6.467396e+03 5.820387e+02 1.403425e+06 9.150018e+09 217
  37. 0b0b0ce8 7372800 2.621440e+08 2.828637e+02 4.132770e+01 2.376055e+04 6.864469e+06 84
  38. 4220e23d 29491200 2.097152e+09 2.091138e+03 2.430963e+02 3.764048e+05 7.977516e+08 180
  39. 87a7dc42 149299200 2.388787e+10 2.171545e+04 9.979353e+02 3.431041e+06 7.466394e+10 158
  40. ####################
  41. # COMB_0
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 3
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda3_impl0 (Comb0)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 492beed5 66355200 7.077888e+09 6.530201e+03 6.982602e+02 1.214617e+06 8.022384e+09 186
  69. 0b0b0ce8 7372800 2.621440e+08 2.596160e+02 3.720670e+01 2.907699e+04 7.703898e+06 112
  70. 4220e23d 29491200 2.097152e+09 2.068075e+03 2.561461e+02 4.156832e+05 8.728519e+08 201
  71. 87a7dc42 149299200 2.388787e+10 2.178854e+04 1.485331e+03 3.355435e+06 7.344977e+10 154
  72. ####################
  73. # COMB_1
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 1
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda1_impl0 (Comb1)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 492beed5 66355200 7.077888e+09 6.594324e+03 6.341124e+02 1.384808e+06 9.216313e+09 210
  101. 0b0b0ce8 7372800 2.621440e+08 2.592059e+02 3.728165e+01 2.773503e+04 7.337807e+06 107
  102. 4220e23d 29491200 2.097152e+09 2.149687e+03 2.853500e+02 3.847940e+05 8.417616e+08 179
  103. 87a7dc42 149299200 2.388787e+10 2.210351e+04 9.525598e+02 3.426044e+06 7.586825e+10 155
  104. ####################
  105. # COMB_3
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 2
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda2_impl0 (Comb3)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 492beed5 66355200 7.077888e+09 6.615698e+03 6.959563e+02 1.210673e+06 8.098082e+09 183
  133. 0b0b0ce8 7372800 2.621440e+08 2.665077e+02 3.721734e+01 3.278045e+04 8.906615e+06 123
  134. 4220e23d 29491200 2.097152e+09 2.090283e+03 2.730830e+02 4.285080e+05 9.109906e+08 205
  135. 87a7dc42 149299200 2.388787e+10 2.206407e+04 1.175820e+03 3.397867e+06 7.518367e+10 154
  136. ####################
  137. # COMB_4
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 0
  144. ####################
  145. # DEV_0
  146. # device id
  147. 0
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cpu0_impl0 (Comb4)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 492beed5 66355200 7.077888e+09 2.793361e+05 4.545353e+04 2.039154e+07 5.846913e+12 73
  165. 0b0b0ce8 7372800 2.621440e+08 1.003329e+04 9.763114e+02 3.471519e+06 3.516056e+10 346
  166. 4220e23d 29491200 2.097152e+09 8.266143e+04 1.577004e+04 6.860899e+06 5.877733e+11 83
  167. 87a7dc42 149299200 2.388787e+10 9.422627e+05 1.729617e+05 1.517043e+08 1.477617e+14 161