starpu_slu_lu_model_22.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 8cfc3ba0 24883200 0.000000e+00 1.164877e+05 2.576301e+04 2.054842e+08 2.510721e+13 1764
  37. f0ac7beb 4915200 0.000000e+00 1.087142e+04 2.109400e+03 2.505863e+07 2.826792e+11 2305
  38. d46431bb 1228800 0.000000e+00 1.613402e+03 3.115535e+02 8.438094e+06 1.412169e+10 5230
  39. 24c84a50 11059200 0.000000e+00 3.517390e+04 7.045528e+03 6.925741e+07 2.533794e+12 1969
  40. ####################
  41. # COMB_1
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 0
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda0_impl0 (Comb1)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 8cfc3ba0 24883200 0.000000e+00 2.688252e+03 2.597845e+02 1.459721e+07 3.960743e+10 5430
  69. f0ac7beb 4915200 0.000000e+00 2.657700e+02 2.996380e+01 1.356225e+06 3.650255e+08 5103
  70. d46431bb 1228800 0.000000e+00 6.142508e+01 1.012391e+01 4.393736e+05 2.772170e+07 7153
  71. 24c84a50 11059200 0.000000e+00 7.851775e+02 4.684799e+01 4.315336e+06 3.400367e+09 5496
  72. ####################
  73. # COMB_0
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 2
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda2_impl0 (Comb0)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 8cfc3ba0 24883200 0.000000e+00 2.707789e+03 2.773178e+02 1.421860e+07 3.890480e+10 5251
  101. f0ac7beb 4915200 0.000000e+00 2.693001e+02 2.710216e+01 1.308798e+06 3.560293e+08 4860
  102. d46431bb 1228800 0.000000e+00 6.592485e+01 1.426453e+01 1.071279e+05 7.393038e+06 1625
  103. 24c84a50 11059200 0.000000e+00 7.926860e+02 4.760061e+01 4.363736e+06 3.471546e+09 5505
  104. ####################
  105. # COMB_2
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 1
  112. ####################
  113. # DEV_0
  114. # device id
  115. 1
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cuda1_impl0 (Comb2)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 8cfc3ba0 24883200 0.000000e+00 2.706383e+03 2.631153e+02 1.444938e+07 3.947516e+10 5339
  133. f0ac7beb 4915200 0.000000e+00 2.686331e+02 2.912062e+01 1.401996e+06 3.810483e+08 5219
  134. d46431bb 1228800 0.000000e+00 6.317490e+01 1.087216e+01 2.866877e+05 1.864788e+07 4538
  135. 24c84a50 11059200 0.000000e+00 7.922324e+02 5.091772e+01 4.156844e+06 3.306790e+09 5247
  136. ####################
  137. # COMB_3
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 3
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda3_impl0 (Comb3)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 8cfc3ba0 24883200 0.000000e+00 2.681149e+03 2.665822e+02 1.451306e+07 3.929636e+10 5413
  165. f0ac7beb 4915200 0.000000e+00 2.642224e+02 2.666799e+01 1.450317e+06 3.871098e+08 5489
  166. d46431bb 1228800 0.000000e+00 5.975719e+01 9.345113e+00 4.033610e+05 2.469321e+07 6750
  167. 24c84a50 11059200 0.000000e+00 7.867204e+02 4.699968e+01 4.148377e+06 3.275261e+09 5273