save_cl_bottom.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 4af260f6 14678040 0.000000e+00 2.985465e+01 6.158621e+00 3.552703e+03 1.105782e+05 119
  37. fb4b8624 4427800 0.000000e+00 1.132689e+01 2.249702e+00 2.423954e+03 2.853894e+04 214
  38. f2ff9ae5 34480152 0.000000e+00 5.622304e+01 1.121739e+01 9.276802e+03 5.423319e+05 165
  39. ####################
  40. # COMB_2
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb2)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 4af260f6 14678040 0.000000e+00 2.632587e+01 4.244468e+00 1.174134e+04 3.171360e+05 446
  68. fb4b8624 4427800 0.000000e+00 2.560067e+01 2.946464e+00 6.809779e+03 1.766442e+05 266
  69. f2ff9ae5 34480152 0.000000e+00 2.687395e+01 3.041318e+00 1.378634e+04 3.752385e+05 513
  70. ####################
  71. # COMB_6
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 3
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda3_impl0 (Comb6)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 4af260f6 14678040 0.000000e+00 2.682825e+01 3.688517e+00 9.309402e+03 2.544759e+05 347
  99. fb4b8624 4427800 0.000000e+00 2.601287e+01 3.034296e+00 6.711320e+03 1.769561e+05 258
  100. f2ff9ae5 34480152 0.000000e+00 2.650277e+01 3.250317e+00 1.327789e+04 3.571937e+05 501
  101. ####################
  102. # COMB_5
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 0
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda0_impl0 (Comb5)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 4af260f6 14678040 0.000000e+00 2.844841e+01 4.987346e+00 1.118023e+04 3.278350e+05 393
  130. fb4b8624 4427800 0.000000e+00 2.545228e+01 3.038424e+00 7.533874e+03 1.944869e+05 296
  131. f2ff9ae5 34480152 0.000000e+00 2.671593e+01 2.977811e+00 9.510870e+03 2.572485e+05 356
  132. ####################
  133. # COMB_7
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 5
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda5_impl0 (Comb7)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 4af260f6 14678040 0.000000e+00 2.683154e+01 3.643920e+00 1.145707e+04 3.130806e+05 427
  161. fb4b8624 4427800 0.000000e+00 2.439165e+01 2.519213e+00 6.951620e+03 1.713702e+05 285
  162. f2ff9ae5 34480152 0.000000e+00 2.686670e+01 3.337051e+00 1.332588e+04 3.635460e+05 496
  163. ####################
  164. # COMB_8
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 7
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda7_impl0 (Comb8)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 4af260f6 14678040 0.000000e+00 2.743422e+01 5.313897e+00 8.504608e+03 2.420709e+05 310
  192. fb4b8624 4427800 0.000000e+00 2.591823e+01 3.009457e+00 7.879143e+03 2.069667e+05 304
  193. f2ff9ae5 34480152 0.000000e+00 2.671837e+01 2.963498e+00 1.282482e+04 3.468736e+05 480
  194. ####################
  195. # COMB_1
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 4
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda4_impl0 (Comb1)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 4af260f6 14678040 0.000000e+00 2.572873e+01 2.716127e+00 1.232406e+04 3.206163e+05 479
  223. fb4b8624 4427800 0.000000e+00 2.555023e+01 2.989409e+00 6.362008e+03 1.647760e+05 249
  224. f2ff9ae5 34480152 0.000000e+00 2.648407e+01 2.593556e+00 1.504295e+04 4.022192e+05 568
  225. ####################
  226. # COMB_4
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 6
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda6_impl0 (Comb4)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 4af260f6 14678040 0.000000e+00 2.535931e+01 2.801001e+00 7.303480e+03 1.874707e+05 288
  254. fb4b8624 4427800 0.000000e+00 2.706983e+01 4.764143e+00 1.228970e+04 3.429847e+05 454
  255. f2ff9ae5 34480152 0.000000e+00 2.645378e+01 3.704623e+00 1.251264e+04 3.374982e+05 473
  256. ####################
  257. # COMB_3
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 2
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda2_impl0 (Comb3)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 4af260f6 14678040 0.000000e+00 2.565071e+01 2.881053e+00 1.064505e+04 2.764977e+05 415
  285. fb4b8624 4427800 0.000000e+00 2.622930e+01 4.388391e+00 8.262230e+03 2.227788e+05 315
  286. f2ff9ae5 34480152 0.000000e+00 2.628917e+01 2.974884e+00 1.204044e+04 3.205863e+05 458