chol_model_22.idgraf 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 24c84a50 11059200 1.769472e+09 8.987520e+04 9.682708e+02 2.085105e+07 1.874210e+12 232
  37. d46431bb 1228800 6.553600e+07 3.465410e+03 7.427679e+01 2.737674e+06 9.491521e+09 790
  38. f0ac7beb 4915200 5.242880e+08 2.744657e+04 5.713498e+02 7.575252e+06 2.080048e+11 276
  39. ####################
  40. # COMB_4
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb4)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 24c84a50 11059200 1.769472e+09 2.825219e+03 1.227364e+02 1.106356e+07 3.131597e+10 3916
  68. d46431bb 1228800 6.553600e+07 2.060677e+02 2.909125e+01 5.497887e+05 1.155516e+08 2668
  69. f0ac7beb 4915200 5.242880e+08 9.076961e+02 5.977819e+01 3.441076e+06 3.136998e+09 3791
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 3
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda3_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 24c84a50 11059200 1.769472e+09 2.823818e+03 1.560928e+02 1.063450e+07 3.012164e+10 3766
  99. d46431bb 1228800 6.553600e+07 1.632767e+02 2.137437e+01 5.224853e+05 8.677162e+07 3200
  100. f0ac7beb 4915200 5.242880e+08 9.226606e+02 6.080500e+01 3.410153e+06 3.160079e+09 3696
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb3)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 24c84a50 11059200 1.769472e+09 2.821988e+03 1.631366e+02 1.046111e+07 2.961977e+10 3707
  130. d46431bb 1228800 6.553600e+07 1.661504e+02 2.199315e+01 5.172263e+05 8.744312e+07 3113
  131. f0ac7beb 4915200 5.242880e+08 9.172785e+02 5.967474e+01 3.492079e+06 3.216766e+09 3807
  132. ####################
  133. # COMB_1
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb1)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 24c84a50 11059200 1.769472e+09 2.817019e+03 1.506473e+02 1.119202e+07 3.161828e+10 3973
  161. d46431bb 1228800 6.553600e+07 2.042642e+02 2.707555e+01 5.498791e+05 1.142941e+08 2692
  162. f0ac7beb 4915200 5.242880e+08 9.044446e+02 5.780357e+01 3.477590e+06 3.158134e+09 3845
  163. ####################
  164. # COMB_7
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 4
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda4_impl0 (Comb7)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 24c84a50 11059200 1.769472e+09 2.816710e+03 1.414989e+02 1.032888e+07 2.916687e+10 3667
  192. d46431bb 1228800 6.553600e+07 1.639497e+02 2.257894e+01 4.474187e+05 7.474542e+07 2729
  193. f0ac7beb 4915200 5.242880e+08 9.331501e+02 5.611510e+01 3.235231e+06 3.029874e+09 3467
  194. ####################
  195. # COMB_5
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 6
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda6_impl0 (Comb5)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 24c84a50 11059200 1.769472e+09 2.815225e+03 1.445443e+02 1.009821e+07 2.850368e+10 3587
  223. d46431bb 1228800 6.553600e+07 1.659035e+02 2.475202e+01 4.006569e+05 6.794997e+07 2415
  224. f0ac7beb 4915200 5.242880e+08 9.137585e+02 6.301297e+01 3.125968e+06 2.869963e+09 3421
  225. ####################
  226. # COMB_8
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 5
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda5_impl0 (Comb8)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 24c84a50 11059200 1.769472e+09 2.807699e+03 1.292512e+02 1.006279e+07 2.831317e+10 3584
  254. d46431bb 1228800 6.553600e+07 1.680450e+02 2.634123e+01 3.922170e+05 6.752957e+07 2334
  255. f0ac7beb 4915200 5.242880e+08 8.912551e+02 5.629783e+01 3.090873e+06 2.765747e+09 3468
  256. ####################
  257. # COMB_6
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 7
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda7_impl0 (Comb6)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 24c84a50 11059200 1.769472e+09 2.827622e+03 1.304764e+02 1.027841e+07 2.912533e+10 3635
  285. d46431bb 1228800 6.553600e+07 1.666216e+02 2.357918e+01 4.083895e+05 6.940921e+07 2451
  286. f0ac7beb 4915200 5.242880e+08 9.077285e+02 5.688987e+01 3.089908e+06 2.815814e+09 3404