starpu_slu_lu_model_12.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_8
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb8)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 2c1922b7 819200 0.000000e+00 2.469013e+03 5.595193e+01 2.765294e+05 6.831054e+08 112
  37. d39bff17 3276800 0.000000e+00 1.667528e+04 1.964808e+02 1.300672e+06 2.169208e+10 78
  38. ff82dda0 7372800 0.000000e+00 5.216745e+04 4.664151e+02 3.443052e+06 1.796296e+11 66
  39. ####################
  40. # COMB_5
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb5)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 2c1922b7 819200 0.000000e+00 7.490410e+02 1.344248e+02 7.415506e+04 5.733412e+07 99
  68. d39bff17 3276800 0.000000e+00 2.737524e+03 2.974057e+02 3.942034e+05 1.091878e+09 144
  69. ff82dda0 7372800 0.000000e+00 7.212728e+03 1.319942e+03 6.924219e+05 5.161506e+09 96
  70. ####################
  71. # COMB_6
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 3
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda3_impl0 (Comb6)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 2c1922b7 819200 0.000000e+00 7.688939e+02 1.457751e+02 6.843156e+04 5.450789e+07 89
  99. d39bff17 3276800 0.000000e+00 2.735563e+03 2.889694e+02 2.899697e+05 8.020820e+08 106
  100. ff82dda0 7372800 0.000000e+00 6.820126e+03 9.314994e+02 7.638542e+05 5.306763e+09 112
  101. ####################
  102. # COMB_2
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 5
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda5_impl0 (Comb2)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 2c1922b7 819200 0.000000e+00 7.150281e+02 1.235393e+02 6.363750e+04 4.686092e+07 89
  130. d39bff17 3276800 0.000000e+00 2.835249e+03 4.125186e+02 1.899617e+05 5.499903e+08 67
  131. ff82dda0 7372800 0.000000e+00 6.720945e+03 7.632032e+02 6.989783e+05 4.758372e+09 104
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 7
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda7_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 2c1922b7 819200 0.000000e+00 7.190609e+02 1.144317e+02 7.406327e+04 5.460474e+07 103
  161. d39bff17 3276800 0.000000e+00 2.867186e+03 4.168496e+02 2.838514e+05 8.310575e+08 99
  162. ff82dda0 7372800 0.000000e+00 6.809425e+03 9.031920e+02 6.400859e+05 4.435298e+09 94
  163. ####################
  164. # COMB_0
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 4
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda4_impl0 (Comb0)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 2c1922b7 819200 0.000000e+00 7.136273e+02 1.258701e+02 7.350362e+04 5.408605e+07 103
  192. d39bff17 3276800 0.000000e+00 2.942246e+03 4.585544e+02 1.706502e+05 5.142907e+08 58
  193. ff82dda0 7372800 0.000000e+00 6.744194e+03 8.416374e+02 5.597681e+05 3.833978e+09 83
  194. ####################
  195. # COMB_7
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 2
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda2_impl0 (Comb7)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 2c1922b7 819200 0.000000e+00 7.204798e+02 9.746533e+01 1.080720e+05 7.928859e+07 150
  223. d39bff17 3276800 0.000000e+00 2.539831e+03 4.296517e+02 3.885942e+05 1.015208e+09 153
  224. ff82dda0 7372800 0.000000e+00 7.293979e+03 1.385713e+03 6.929280e+05 5.236621e+09 95
  225. ####################
  226. # COMB_1
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 6
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda6_impl0 (Comb1)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 2c1922b7 819200 0.000000e+00 7.460951e+02 1.203288e+02 7.386342e+04 5.654256e+07 99
  254. d39bff17 3276800 0.000000e+00 2.972783e+03 5.066224e+02 2.259315e+05 6.911522e+08 76
  255. ff82dda0 7372800 0.000000e+00 6.643349e+03 8.230064e+02 6.510482e+05 4.391520e+09 98
  256. ####################
  257. # COMB_3
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 0
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda0_impl0 (Comb3)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 2c1922b7 819200 0.000000e+00 7.518059e+02 1.406096e+02 8.495406e+04 6.610309e+07 113
  285. d39bff17 3276800 0.000000e+00 2.794983e+03 3.357608e+02 4.164524e+05 1.180775e+09 149
  286. ff82dda0 7372800 0.000000e+00 6.735838e+03 7.525487e+02 6.803197e+05 4.639723e+09 101