chol_model_21.mirage 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 4
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 1
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 7372800 8.856576e+08 4.564676e+04 7.031596e+02 5.687586e+07 2.596815e+12 1246
  37. ####################
  38. # COMB_1
  39. # number of types devices
  40. 1
  41. ####################
  42. # DEV_0
  43. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  44. 1
  45. ####################
  46. # DEV_0
  47. # device id
  48. 0
  49. ####################
  50. # DEV_0
  51. # number of cores
  52. 1
  53. ##########
  54. # number of implementations
  55. 1
  56. #####
  57. # Model for cuda0_impl0 (Comb1)
  58. # number of entries
  59. 1
  60. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  61. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  62. # a b c
  63. nan nan nan
  64. # hash size flops mean (us) dev (us) sum sum2 n
  65. ff82dda0 7372800 8.856576e+08 6.393638e+03 3.362739e+02 3.650767e+06 2.340625e+10 571
  66. ####################
  67. # COMB_2
  68. # number of types devices
  69. 1
  70. ####################
  71. # DEV_0
  72. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  73. 1
  74. ####################
  75. # DEV_0
  76. # device id
  77. 1
  78. ####################
  79. # DEV_0
  80. # number of cores
  81. 1
  82. ##########
  83. # number of implementations
  84. 1
  85. #####
  86. # Model for cuda1_impl0 (Comb2)
  87. # number of entries
  88. 1
  89. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  90. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  91. # a b c
  92. nan nan nan
  93. # hash size flops mean (us) dev (us) sum sum2 n
  94. ff82dda0 7372800 8.856576e+08 6.416842e+03 2.746569e+02 2.951747e+06 1.897560e+10 460
  95. ####################
  96. # COMB_3
  97. # number of types devices
  98. 1
  99. ####################
  100. # DEV_0
  101. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  102. 1
  103. ####################
  104. # DEV_0
  105. # device id
  106. 2
  107. ####################
  108. # DEV_0
  109. # number of cores
  110. 1
  111. ##########
  112. # number of implementations
  113. 1
  114. #####
  115. # Model for cuda2_impl0 (Comb3)
  116. # number of entries
  117. 1
  118. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  119. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  120. # a b c
  121. nan nan nan
  122. # hash size flops mean (us) dev (us) sum sum2 n
  123. ff82dda0 7372800 8.856576e+08 6.409443e+03 3.434222e+02 3.243178e+06 2.084664e+10 506