starpu_slu_lu_model_21.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_8
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb8)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 2c1922b7 819200 0.000000e+00 1.946809e+03 8.216247e+01 4.049363e+05 7.897378e+08 208
  37. d39bff17 3276800 0.000000e+00 1.423970e+04 2.281585e+02 1.395491e+06 1.987647e+10 98
  38. ff82dda0 7372800 0.000000e+00 4.640991e+04 5.437505e+02 4.919451e+06 2.283426e+11 106
  39. ####################
  40. # COMB_0
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 4
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda4_impl0 (Comb0)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 2c1922b7 819200 0.000000e+00 4.484181e+02 9.807341e+01 3.004401e+04 1.411671e+07 67
  68. d39bff17 3276800 0.000000e+00 1.658665e+03 2.005859e+02 2.388477e+05 4.019622e+08 144
  69. ff82dda0 7372800 0.000000e+00 3.922083e+03 2.271290e+02 2.588575e+05 1.018665e+09 66
  70. ####################
  71. # COMB_3
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 0
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda0_impl0 (Comb3)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 2c1922b7 819200 0.000000e+00 5.042679e+02 1.229686e+02 7.362312e+04 3.933348e+07 146
  99. d39bff17 3276800 0.000000e+00 2.167031e+03 5.827483e+02 2.773800e+05 6.445595e+08 128
  100. ff82dda0 7372800 0.000000e+00 4.035358e+03 4.245106e+02 4.035358e+05 1.646433e+09 100
  101. ####################
  102. # COMB_1
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 6
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda6_impl0 (Comb1)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 2c1922b7 819200 0.000000e+00 4.873044e+02 1.174149e+02 2.631443e+04 1.356760e+07 54
  130. d39bff17 3276800 0.000000e+00 1.705876e+03 1.721886e+02 1.808228e+05 3.116041e+08 106
  131. ff82dda0 7372800 0.000000e+00 3.936492e+03 2.608005e+02 2.440625e+05 9.649671e+08 62
  132. ####################
  133. # COMB_7
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 2
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda2_impl0 (Comb7)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 2c1922b7 819200 0.000000e+00 5.272057e+02 1.307030e+02 5.535660e+04 3.097805e+07 105
  161. d39bff17 3276800 0.000000e+00 1.638590e+03 9.390080e+01 1.163399e+05 1.912593e+08 71
  162. ff82dda0 7372800 0.000000e+00 4.055643e+03 3.711103e+02 4.177313e+05 1.708355e+09 103
  163. ####################
  164. # COMB_2
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 5
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda5_impl0 (Comb2)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 2c1922b7 819200 0.000000e+00 4.303558e+02 7.490536e+01 2.840348e+04 1.259392e+07 66
  192. d39bff17 3276800 0.000000e+00 1.669452e+03 1.444951e+02 1.419035e+05 2.386758e+08 85
  193. ff82dda0 7372800 0.000000e+00 4.288060e+03 7.671104e+02 2.744359e+05 1.214459e+09 64
  194. ####################
  195. # COMB_5
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 1
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda1_impl0 (Comb5)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 2c1922b7 819200 0.000000e+00 4.394264e+02 8.387153e+01 6.283798e+04 2.861859e+07 143
  223. d39bff17 3276800 0.000000e+00 2.098818e+03 5.403136e+02 2.140795e+05 4.790917e+08 102
  224. ff82dda0 7372800 0.000000e+00 4.766912e+03 1.123433e+03 7.579390e+05 3.813703e+09 159
  225. ####################
  226. # COMB_6
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 3
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda3_impl0 (Comb6)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 2c1922b7 819200 0.000000e+00 4.660051e+02 1.021627e+02 6.477470e+04 3.163611e+07 139
  254. d39bff17 3276800 0.000000e+00 2.103985e+03 5.293854e+02 2.377503e+05 5.318912e+08 113
  255. ff82dda0 7372800 0.000000e+00 3.972257e+03 3.858968e+02 2.899747e+05 1.162725e+09 73
  256. ####################
  257. # COMB_4
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 7
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda7_impl0 (Comb4)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 2c1922b7 819200 0.000000e+00 5.222345e+02 1.241013e+02 2.715620e+04 1.498276e+07 52
  285. d39bff17 3276800 0.000000e+00 1.941135e+03 4.386059e+02 1.824667e+05 3.722759e+08 94
  286. ff82dda0 7372800 0.000000e+00 4.892155e+03 1.147723e+03 2.397156e+05 1.237272e+09 49