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starpu_sgemm_gemm.idgraf

starpu_sgemm_gemm.idgraf 8.7 KB
文件歷史 原始文件

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297 
  1. ##################
    2. 

  2. # Performance Model Version
    3. 

  3. 44
    4. 

  4. 

  5. ####################
    6. 

  6. # COMBs
    7. 

  7. # number of combinations
    8. 

  8. 9
    9. 

  9. ####################
    10. 

  10. # COMB_2
    11. 

  11. # number of types devices
    12. 

  12. 1
    13. 

  13. ####################
    14. 

  14. # DEV_0
    15. 

  15. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    16. 

  16. 1
    17. 

  17. ####################
    18. 

  18. # DEV_0
    19. 

  19. # device id 
    20. 

  20. 0
    21. 

  21. ####################
    22. 

  22. # DEV_0
    23. 

  23. # number of cores 
    24. 

  24. 1
    25. 

  25. ##########
    26. 

  26. # number of implementations
    27. 

  27. 1
    28. 

  28. #####
    29. 

  29. # Model for cuda0_impl0 (Comb2)
    30. 

  30. # number of entries
    31. 

  31. 3
    32. 

  32. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    33. 

  33. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    34. 

  34. # a		b		c
    35. 

  35. nan            	nan            	nan            
    36. 

  36. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    37. 

  37. 0b0b0ce8	3686400        	2.621440e+08   	6.801013e+02   	7.013561e+01   	4.760709e+04   	3.272198e+07   	70
    38. 

  38. 4220e23d	14745600       	2.097152e+09   	5.623635e+03   	5.419920e+02   	4.442672e+05   	2.521603e+09   	79
    39. 

  39. 492beed5	33177600       	7.077888e+09   	1.150361e+04   	5.884814e+02   	1.000814e+06   	1.154310e+10   	87
    40. 

  40. 

  41. ####################
    42. 

  42. # COMB_4
    43. 

  43. # number of types devices
    44. 

  44. 1
    45. 

  45. ####################
    46. 

  46. # DEV_0
    47. 

  47. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    48. 

  48. 1
    49. 

  49. ####################
    50. 

  50. # DEV_0
    51. 

  51. # device id 
    52. 

  52. 1
    53. 

  53. ####################
    54. 

  54. # DEV_0
    55. 

  55. # number of cores 
    56. 

  56. 1
    57. 

  57. ##########
    58. 

  58. # number of implementations
    59. 

  59. 1
    60. 

  60. #####
    61. 

  61. # Model for cuda1_impl0 (Comb4)
    62. 

  62. # number of entries
    63. 

  63. 3
    64. 

  64. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    65. 

  65. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    66. 

  66. # a		b		c
    67. 

  67. nan            	nan            	nan            
    68. 

  68. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    69. 

  69. 0b0b0ce8	3686400        	2.621440e+08   	6.717051e+02   	6.137607e+01   	4.500424e+04   	3.048197e+07   	67
    70. 

  70. 4220e23d	14745600       	2.097152e+09   	5.648275e+03   	4.677390e+02   	4.575103e+05   	2.601865e+09   	81
    71. 

  71. 492beed5	33177600       	7.077888e+09   	1.157020e+04   	6.521027e+02   	1.018178e+06   	1.181795e+10   	88
    72. 

  72. 

  73. ####################
    74. 

  74. # COMB_6
    75. 

  75. # number of types devices
    76. 

  76. 1
    77. 

  77. ####################
    78. 

  78. # DEV_0
    79. 

  79. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    80. 

  80. 1
    81. 

  81. ####################
    82. 

  82. # DEV_0
    83. 

  83. # device id 
    84. 

  84. 2
    85. 

  85. ####################
    86. 

  86. # DEV_0
    87. 

  87. # number of cores 
    88. 

  88. 1
    89. 

  89. ##########
    90. 

  90. # number of implementations
    91. 

  91. 1
    92. 

  92. #####
    93. 

  93. # Model for cuda2_impl0 (Comb6)
    94. 

  94. # number of entries
    95. 

  95. 3
    96. 

  96. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    97. 

  97. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    98. 

  98. # a		b		c
    99. 

  99. nan            	nan            	nan            
    100. 

  100. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    101. 

  101. 0b0b0ce8	3686400        	2.621440e+08   	6.265559e+02   	5.536840e+01   	4.824481e+04   	3.046412e+07   	77
    102. 

  102. 4220e23d	14745600       	2.097152e+09   	5.631203e+03   	4.767455e+02   	4.561275e+05   	2.586957e+09   	81
    103. 

  103. 492beed5	33177600       	7.077888e+09   	1.162826e+04   	6.757302e+02   	1.023286e+06   	1.193922e+10   	88
    104. 

  104. 

  105. ####################
    106. 

  106. # COMB_7
    107. 

  107. # number of types devices
    108. 

  108. 1
    109. 

  109. ####################
    110. 

  110. # DEV_0
    111. 

  111. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    112. 

  112. 1
    113. 

  113. ####################
    114. 

  114. # DEV_0
    115. 

  115. # device id 
    116. 

  116. 3
    117. 

  117. ####################
    118. 

  118. # DEV_0
    119. 

  119. # number of cores 
    120. 

  120. 1
    121. 

  121. ##########
    122. 

  122. # number of implementations
    123. 

  123. 1
    124. 

  124. #####
    125. 

  125. # Model for cuda3_impl0 (Comb7)
    126. 

  126. # number of entries
    127. 

  127. 3
    128. 

  128. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    129. 

  129. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    130. 

  130. # a		b		c
    131. 

  131. nan            	nan            	nan            
    132. 

  132. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    133. 

  133. 0b0b0ce8	3686400        	2.621440e+08   	6.780899e+02   	4.241206e+01   	4.543202e+04   	3.092751e+07   	67
    134. 

  134. 4220e23d	14745600       	2.097152e+09   	5.857201e+03   	8.346836e+02   	4.744333e+05   	2.835284e+09   	81
    135. 

  135. 492beed5	33177600       	7.077888e+09   	1.150498e+04   	4.254093e+02   	9.894285e+05   	1.139892e+10   	86
    136. 

  136. 

  137. ####################
    138. 

  138. # COMB_0
    139. 

  139. # number of types devices
    140. 

  140. 1
    141. 

  141. ####################
    142. 

  142. # DEV_0
    143. 

  143. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    144. 

  144. 1
    145. 

  145. ####################
    146. 

  146. # DEV_0
    147. 

  147. # device id 
    148. 

  148. 4
    149. 

  149. ####################
    150. 

  150. # DEV_0
    151. 

  151. # number of cores 
    152. 

  152. 1
    153. 

  153. ##########
    154. 

  154. # number of implementations
    155. 

  155. 1
    156. 

  156. #####
    157. 

  157. # Model for cuda4_impl0 (Comb0)
    158. 

  158. # number of entries
    159. 

  159. 3
    160. 

  160. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    161. 

  161. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    162. 

  162. # a		b		c
    163. 

  163. nan            	nan            	nan            
    164. 

  164. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    165. 

  165. 0b0b0ce8	3686400        	2.621440e+08   	6.759139e+02   	4.092799e+01   	4.190666e+04   	2.842915e+07   	62
    166. 

  166. 4220e23d	14745600       	2.097152e+09   	5.527477e+03   	2.733928e+02   	4.421982e+05   	2.450220e+09   	80
    167. 

  167. 492beed5	33177600       	7.077888e+09   	1.146770e+04   	1.768909e+02   	1.100899e+06   	1.262778e+10   	96
    168. 

  168. 

  169. ####################
    170. 

  170. # COMB_1
    171. 

  171. # number of types devices
    172. 

  172. 1
    173. 

  173. ####################
    174. 

  174. # DEV_0
    175. 

  175. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    176. 

  176. 1
    177. 

  177. ####################
    178. 

  178. # DEV_0
    179. 

  179. # device id 
    180. 

  180. 5
    181. 

  181. ####################
    182. 

  182. # DEV_0
    183. 

  183. # number of cores 
    184. 

  184. 1
    185. 

  185. ##########
    186. 

  186. # number of implementations
    187. 

  187. 1
    188. 

  188. #####
    189. 

  189. # Model for cuda5_impl0 (Comb1)
    190. 

  190. # number of entries
    191. 

  191. 3
    192. 

  192. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    193. 

  193. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    194. 

  194. # a		b		c
    195. 

  195. nan            	nan            	nan            
    196. 

  196. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    197. 

  197. 0b0b0ce8	3686400        	2.621440e+08   	6.339465e+02   	7.125158e+01   	4.184047e+04   	2.685969e+07   	66
    198. 

  198. 4220e23d	14745600       	2.097152e+09   	5.624130e+03   	4.755864e+02   	4.668028e+05   	2.644133e+09   	83
    199. 

  199. 492beed5	33177600       	7.077888e+09   	1.149102e+04   	5.375188e+02   	1.114629e+06   	1.283625e+10   	97
    200. 

  200. 

  201. ####################
    202. 

  202. # COMB_3
    203. 

  203. # number of types devices
    204. 

  204. 1
    205. 

  205. ####################
    206. 

  206. # DEV_0
    207. 

  207. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    208. 

  208. 1
    209. 

  209. ####################
    210. 

  210. # DEV_0
    211. 

  211. # device id 
    212. 

  212. 6
    213. 

  213. ####################
    214. 

  214. # DEV_0
    215. 

  215. # number of cores 
    216. 

  216. 1
    217. 

  217. ##########
    218. 

  218. # number of implementations
    219. 

  219. 1
    220. 

  220. #####
    221. 

  221. # Model for cuda6_impl0 (Comb3)
    222. 

  222. # number of entries
    223. 

  223. 3
    224. 

  224. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    225. 

  225. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    226. 

  226. # a		b		c
    227. 

  227. nan            	nan            	nan            
    228. 

  228. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    229. 

  229. 0b0b0ce8	3686400        	2.621440e+08   	6.389750e+02   	8.615382e+01   	4.728415e+04   	3.076266e+07   	74
    230. 

  230. 4220e23d	14745600       	2.097152e+09   	5.648331e+03   	5.220897e+02   	4.631632e+05   	2.638450e+09   	82
    231. 

  231. 492beed5	33177600       	7.077888e+09   	1.155069e+04   	5.660846e+02   	1.108866e+06   	1.283893e+10   	96
    232. 

  232. 

  233. ####################
    234. 

  234. # COMB_5
    235. 

  235. # number of types devices
    236. 

  236. 1
    237. 

  237. ####################
    238. 

  238. # DEV_0
    239. 

  239. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    240. 

  240. 1
    241. 

  241. ####################
    242. 

  242. # DEV_0
    243. 

  243. # device id 
    244. 

  244. 7
    245. 

  245. ####################
    246. 

  246. # DEV_0
    247. 

  247. # number of cores 
    248. 

  248. 1
    249. 

  249. ##########
    250. 

  250. # number of implementations
    251. 

  251. 1
    252. 

  252. #####
    253. 

  253. # Model for cuda7_impl0 (Comb5)
    254. 

  254. # number of entries
    255. 

  255. 3
    256. 

  256. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    257. 

  257. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    258. 

  258. # a		b		c
    259. 

  259. nan            	nan            	nan            
    260. 

  260. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    261. 

  261. 0b0b0ce8	3686400        	2.621440e+08   	6.386625e+02   	8.094896e+01   	4.342905e+04   	2.818209e+07   	68
    262. 

  262. 4220e23d	14745600       	2.097152e+09   	5.638657e+03   	3.709019e+02   	4.454539e+05   	2.522630e+09   	79
    263. 

  263. 492beed5	33177600       	7.077888e+09   	1.144012e+04   	2.531108e+02   	1.109691e+06   	1.270122e+10   	97
    264. 

  264. 

  265. ####################
    266. 

  266. # COMB_8
    267. 

  267. # number of types devices
    268. 

  268. 1
    269. 

  269. ####################
    270. 

  270. # DEV_0
    271. 

  271. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
    272. 

  272. 0
    273. 

  273. ####################
    274. 

  274. # DEV_0
    275. 

  275. # device id 
    276. 

  276. 0
    277. 

  277. ####################
    278. 

  278. # DEV_0
    279. 

  279. # number of cores 
    280. 

  280. 1
    281. 

  281. ##########
    282. 

  282. # number of implementations
    283. 

  283. 1
    284. 

  284. #####
    285. 

  285. # Model for cpu0_impl0 (Comb8)
    286. 

  286. # number of entries
    287. 

  287. 3
    288. 

  288. # sumlnx	sumlnx2		sumlny		sumlnxlny	alpha		beta		n	minx		maxx
    289. 

  289. 0.000000e+00   	0.000000e+00   	0.000000e+00   	0.000000e+00   	nan            	nan            	0	0              	0              
    290. 

  290. # a		b		c
    291. 

  291. nan            	nan            	nan            
    292. 

  292. # hash		size		flops		mean (us)	dev (us)	sum		sum2		n
    293. 

  293. 0b0b0ce8	3686400        	2.621440e+08   	1.414338e+04   	6.441210e+02   	3.535844e+05   	5.011251e+09   	25
    294. 

  294. 4220e23d	14745600       	2.097152e+09   	1.091117e+05   	2.701159e+03   	3.382462e+06   	3.692924e+11   	31
    295. 

  295. 492beed5	33177600       	7.077888e+09   	3.621356e+05   	7.764608e+03   	8.329119e+06   	3.017657e+12   	23
    296. 

  296. 

  297.