starpu_dlu_lu_model_22.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_1
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 3
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda3_impl0 (Comb1)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 24c84a50 22118400 0.000000e+00 5.901996e+03 2.140574e+02 2.574451e+07 1.521439e+11 4362
  37. f0ac7beb 9830400 0.000000e+00 1.855425e+03 1.035707e+02 7.464374e+06 1.389274e+10 4023
  38. d46431bb 2457600 0.000000e+00 2.667843e+02 3.133790e+01 9.321442e+05 2.521128e+08 3494
  39. ####################
  40. # COMB_0
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 4
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda4_impl0 (Comb0)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 24c84a50 22118400 0.000000e+00 5.924812e+03 2.030546e+02 2.715934e+07 1.611030e+11 4584
  68. f0ac7beb 9830400 0.000000e+00 1.850857e+03 1.138114e+02 6.774137e+06 1.258537e+10 3660
  69. d46431bb 2457600 0.000000e+00 2.743267e+02 3.237528e+01 7.903352e+05 2.198298e+08 2881
  70. ####################
  71. # COMB_4
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 0
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda0_impl0 (Comb4)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 24c84a50 22118400 0.000000e+00 5.905959e+03 2.324106e+02 2.885061e+07 1.706544e+11 4885
  99. f0ac7beb 9830400 0.000000e+00 1.844033e+03 9.904039e+01 7.516278e+06 1.390024e+10 4076
  100. d46431bb 2457600 0.000000e+00 2.662813e+02 2.651200e+01 1.098144e+06 2.953140e+08 4124
  101. ####################
  102. # COMB_5
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb5)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 24c84a50 22118400 0.000000e+00 5.905860e+03 2.088868e+02 2.619840e+07 1.549176e+11 4436
  130. f0ac7beb 9830400 0.000000e+00 1.843182e+03 9.714398e+01 7.671323e+06 1.417892e+10 4162
  131. d46431bb 2457600 0.000000e+00 2.666213e+02 3.154593e+01 1.003829e+06 2.713890e+08 3765
  132. ####################
  133. # COMB_2
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 1
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda1_impl0 (Comb2)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 24c84a50 22118400 0.000000e+00 5.916743e+03 2.291447e+02 2.686793e+07 1.592091e+11 4541
  161. f0ac7beb 9830400 0.000000e+00 1.837574e+03 9.255327e+01 7.197777e+06 1.326000e+10 3917
  162. d46431bb 2457600 0.000000e+00 2.645367e+02 2.904285e+01 1.078252e+06 2.886751e+08 4076
  163. ####################
  164. # COMB_8
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 0
  171. ####################
  172. # DEV_0
  173. # device id
  174. 0
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cpu0_impl0 (Comb8)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 24c84a50 22118400 0.000000e+00 1.776444e+05 1.603881e+03 1.085407e+08 1.928322e+13 611
  192. f0ac7beb 9830400 0.000000e+00 5.438487e+04 1.553469e+03 1.598915e+07 8.702776e+11 294
  193. d46431bb 2457600 0.000000e+00 6.892168e+03 1.879454e+02 4.218007e+06 2.909283e+10 612
  194. ####################
  195. # COMB_6
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 6
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda6_impl0 (Comb6)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 24c84a50 22118400 0.000000e+00 5.908798e+03 2.191022e+02 2.432652e+07 1.439381e+11 4117
  223. f0ac7beb 9830400 0.000000e+00 1.870298e+03 1.158137e+02 6.306645e+06 1.184053e+10 3372
  224. d46431bb 2457600 0.000000e+00 2.622005e+02 3.221213e+01 7.630036e+05 2.030794e+08 2910
  225. ####################
  226. # COMB_7
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 5
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda5_impl0 (Comb7)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 24c84a50 22118400 0.000000e+00 5.908890e+03 2.133901e+02 2.731089e+07 1.615875e+11 4622
  254. f0ac7beb 9830400 0.000000e+00 1.853662e+03 1.234628e+02 6.493379e+06 1.208993e+10 3503
  255. d46431bb 2457600 0.000000e+00 2.672063e+02 3.249622e+01 7.262666e+05 1.969332e+08 2718
  256. ####################
  257. # COMB_3
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 7
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda7_impl0 (Comb3)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 24c84a50 22118400 0.000000e+00 5.908429e+03 2.149126e+02 2.371053e+07 1.402773e+11 4013
  285. f0ac7beb 9830400 0.000000e+00 1.855601e+03 1.161756e+02 6.509447e+06 1.212628e+10 3508
  286. d46431bb 2457600 0.000000e+00 2.697690e+02 3.186509e+01 7.013994e+05 1.918558e+08 2600