starpu_dlu_lu_model_21.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 14745600 0.000000e+00 6.700359e+03 1.036459e+03 3.886208e+05 2.666205e+09 58
  37. d39bff17 6553600 0.000000e+00 2.067623e+03 3.658691e+02 3.825102e+05 8.156510e+08 185
  38. 2c1922b7 1638400 0.000000e+00 6.344928e+02 1.313164e+02 1.091328e+05 7.220992e+07 172
  39. ####################
  40. # COMB_5
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 2
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda2_impl0 (Comb5)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 14745600 0.000000e+00 6.634729e+03 1.380283e+03 4.777005e+05 3.306586e+09 72
  68. d39bff17 6553600 0.000000e+00 2.102108e+03 3.770829e+02 2.690698e+05 5.838144e+08 128
  69. 2c1922b7 1638400 0.000000e+00 6.251127e+02 1.334964e+02 1.168961e+05 7.640580e+07 187
  70. ####################
  71. # COMB_0
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 4
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda4_impl0 (Comb0)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 14745600 0.000000e+00 5.973111e+03 7.873858e+02 4.420102e+05 2.686054e+09 74
  99. d39bff17 6553600 0.000000e+00 2.088129e+03 3.411148e+02 2.129891e+05 4.566174e+08 102
  100. 2c1922b7 1638400 0.000000e+00 5.816119e+02 1.098601e+02 6.165086e+04 3.713622e+07 106
  101. ####################
  102. # COMB_6
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 6
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda6_impl0 (Comb6)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 14745600 0.000000e+00 5.813439e+03 5.835403e+02 2.441645e+05 1.433737e+09 42
  130. d39bff17 6553600 0.000000e+00 2.170079e+03 5.032568e+02 7.161259e+04 1.637628e+08 33
  131. 2c1922b7 1638400 0.000000e+00 6.080488e+02 1.225789e+02 3.101049e+04 1.962219e+07 51
  132. ####################
  133. # COMB_8
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 0
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cpu0_impl0 (Comb8)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 14745600 0.000000e+00 9.133611e+04 7.141260e+02 1.032098e+07 9.427358e+11 113
  161. d39bff17 6553600 0.000000e+00 2.797330e+04 6.068477e+02 1.482585e+06 4.149232e+10 53
  162. 2c1922b7 1638400 0.000000e+00 3.803279e+03 2.345034e+02 3.308852e+05 1.263233e+09 87
  163. ####################
  164. # COMB_1
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 3
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda3_impl0 (Comb1)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. ff82dda0 14745600 0.000000e+00 6.609495e+03 1.035460e+03 4.296172e+05 2.909244e+09 65
  192. d39bff17 6553600 0.000000e+00 2.129873e+03 3.868465e+02 3.407797e+05 7.497615e+08 160
  193. 2c1922b7 1638400 0.000000e+00 6.443548e+02 1.239934e+02 8.054435e+04 5.382094e+07 125
  194. ####################
  195. # COMB_3
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 7
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda7_impl0 (Comb3)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. ff82dda0 14745600 0.000000e+00 5.938773e+03 5.045720e+02 2.078570e+05 1.243326e+09 35
  223. d39bff17 6553600 0.000000e+00 2.180034e+03 4.239424e+02 1.286220e+05 2.910041e+08 59
  224. 2c1922b7 1638400 0.000000e+00 5.996256e+02 1.220514e+02 5.816368e+04 3.632139e+07 97
  225. ####################
  226. # COMB_7
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 5
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda5_impl0 (Comb7)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. ff82dda0 14745600 0.000000e+00 6.467618e+03 9.651621e+02 2.910428e+05 1.924273e+09 45
  254. d39bff17 6553600 0.000000e+00 2.057931e+03 3.333471e+02 1.872717e+05 3.955042e+08 91
  255. 2c1922b7 1638400 0.000000e+00 6.141799e+02 1.365857e+02 5.159111e+04 3.325329e+07 84
  256. ####################
  257. # COMB_2
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 1
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda1_impl0 (Comb2)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. ff82dda0 14745600 0.000000e+00 6.429538e+03 9.929716e+02 5.015040e+05 3.301346e+09 78
  285. d39bff17 6553600 0.000000e+00 2.056349e+03 3.356881e+02 4.565094e+05 9.637588e+08 222
  286. 2c1922b7 1638400 0.000000e+00 6.374873e+02 1.360140e+02 9.498561e+04 6.330859e+07 149