starpu_dlu_lu_model_12.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_2
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 1
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda1_impl0 (Comb2)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 14745600 0.000000e+00 6.925318e+03 8.376976e+02 5.748014e+05 4.038926e+09 83
  37. d39bff17 6553600 0.000000e+00 2.271937e+03 3.454949e+02 2.340095e+05 5.439496e+08 103
  38. 2c1922b7 1638400 0.000000e+00 7.049814e+02 1.197767e+02 1.254867e+05 9.101946e+07 178
  39. ####################
  40. # COMB_1
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb1)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 14745600 0.000000e+00 7.291615e+03 1.041939e+03 4.593717e+05 3.417957e+09 63
  68. d39bff17 6553600 0.000000e+00 2.282720e+03 4.096195e+02 3.903452e+05 9.197407e+08 171
  69. 2c1922b7 1638400 0.000000e+00 6.999720e+02 1.145665e+02 1.343946e+05 9.659256e+07 192
  70. ####################
  71. # COMB_7
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 5
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda5_impl0 (Comb7)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 14745600 0.000000e+00 7.177388e+03 9.455873e+02 3.947563e+05 2.882497e+09 55
  99. d39bff17 6553600 0.000000e+00 2.335362e+03 3.317057e+02 2.825788e+05 6.732374e+08 121
  100. 2c1922b7 1638400 0.000000e+00 7.266144e+02 9.381637e+01 4.432348e+04 3.274297e+07 61
  101. ####################
  102. # COMB_8
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 0
  109. ####################
  110. # DEV_0
  111. # device id
  112. 0
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cpu0_impl0 (Comb8)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 14745600 0.000000e+00 9.210227e+04 5.563000e+02 1.252591e+07 1.153707e+12 136
  130. d39bff17 6553600 0.000000e+00 2.809162e+04 4.267578e+02 1.573131e+06 4.420199e+10 56
  131. 2c1922b7 1638400 0.000000e+00 3.732094e+03 1.582101e+02 3.993341e+05 1.493031e+09 107
  132. ####################
  133. # COMB_3
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 7
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda7_impl0 (Comb3)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 14745600 0.000000e+00 7.047943e+03 9.923280e+02 4.017327e+05 2.887518e+09 57
  161. d39bff17 6553600 0.000000e+00 2.358363e+03 2.904964e+02 2.381946e+05 5.702726e+08 101
  162. 2c1922b7 1638400 0.000000e+00 7.376273e+02 1.192099e+02 4.425764e+04 3.349831e+07 60
  163. ####################
  164. # COMB_5
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 2
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda2_impl0 (Comb5)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. ff82dda0 14745600 0.000000e+00 7.125894e+03 1.170430e+03 6.769599e+05 4.954085e+09 95
  192. d39bff17 6553600 0.000000e+00 2.913435e+03 7.837592e+02 2.651226e+05 8.283167e+08 91
  193. 2c1922b7 1638400 0.000000e+00 7.396845e+02 1.557697e+02 7.692719e+04 5.942533e+07 104
  194. ####################
  195. # COMB_0
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 4
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda4_impl0 (Comb0)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. ff82dda0 14745600 0.000000e+00 6.906666e+03 1.069281e+03 3.177066e+05 2.246888e+09 46
  223. d39bff17 6553600 0.000000e+00 2.331985e+03 3.108312e+02 2.914982e+05 6.918465e+08 125
  224. 2c1922b7 1638400 0.000000e+00 7.036069e+02 1.117682e+02 5.277052e+04 3.806661e+07 75
  225. ####################
  226. # COMB_6
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 6
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda6_impl0 (Comb6)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. ff82dda0 14745600 0.000000e+00 7.634969e+03 1.278868e+03 4.122883e+05 3.236126e+09 54
  254. d39bff17 6553600 0.000000e+00 2.361692e+03 2.763159e+02 1.747652e+05 4.183915e+08 74
  255. 2c1922b7 1638400 0.000000e+00 7.215132e+02 1.060983e+02 7.287283e+04 5.371565e+07 101
  256. ####################
  257. # COMB_4
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 0
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda0_impl0 (Comb4)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. ff82dda0 14745600 0.000000e+00 7.011366e+03 8.280915e+02 6.871138e+05 4.884809e+09 98
  285. d39bff17 6553600 0.000000e+00 2.294721e+03 3.366230e+02 4.451759e+05 1.043537e+09 194
  286. 2c1922b7 1638400 0.000000e+00 6.840134e+02 1.166270e+02 1.114942e+05 7.848061e+07 163