starpu_dgemm_gemm.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 0b0b0ce8 7372800 2.621440e+08 1.052061e+03 3.198115e+01 6.838395e+04 7.201055e+07 65
  37. 4220e23d 29491200 2.097152e+09 7.092203e+03 4.667104e+02 6.028372e+05 4.293959e+09 85
  38. 492beed5 66355200 7.077888e+09 2.348390e+04 1.879558e+03 2.230970e+06 5.272750e+10 95
  39. ####################
  40. # COMB_3
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb3)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 0b0b0ce8 7372800 2.621440e+08 1.052063e+03 4.974434e+01 7.680058e+04 8.097966e+07 73
  68. 4220e23d 29491200 2.097152e+09 7.169429e+03 6.510141e+02 6.165709e+05 4.456910e+09 86
  69. 492beed5 66355200 7.077888e+09 2.369721e+04 2.666656e+03 2.203840e+06 5.288620e+10 93
  70. ####################
  71. # COMB_4
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 4
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda4_impl0 (Comb4)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 0b0b0ce8 7372800 2.621440e+08 1.073351e+03 1.039589e+02 5.796097e+04 6.279609e+07 54
  99. 4220e23d 29491200 2.097152e+09 7.178253e+03 6.674450e+02 6.245080e+05 4.521634e+09 87
  100. 492beed5 66355200 7.077888e+09 2.322028e+04 3.606800e+02 2.252367e+06 5.231319e+10 97
  101. ####################
  102. # COMB_7
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 5
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda5_impl0 (Comb7)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 0b0b0ce8 7372800 2.621440e+08 1.047275e+03 4.810046e+01 6.074194e+04 6.374769e+07 58
  130. 4220e23d 29491200 2.097152e+09 7.215871e+03 7.571281e+02 6.277808e+05 4.579858e+09 87
  131. 492beed5 66355200 7.077888e+09 2.323291e+04 1.169036e+03 2.230359e+06 5.194892e+10 96
  132. ####################
  133. # COMB_5
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 2
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda2_impl0 (Comb5)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 0b0b0ce8 7372800 2.621440e+08 1.045464e+03 2.548321e+01 6.168239e+04 6.452506e+07 59
  161. 4220e23d 29491200 2.097152e+09 7.130284e+03 4.158059e+02 5.632924e+05 4.030093e+09 79
  162. 492beed5 66355200 7.077888e+09 2.322391e+04 7.530407e+02 2.090152e+06 4.859253e+10 90
  163. ####################
  164. # COMB_2
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 7
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda7_impl0 (Comb2)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 0b0b0ce8 7372800 2.621440e+08 1.058842e+03 8.984549e+01 6.353054e+04 6.775316e+07 60
  192. 4220e23d 29491200 2.097152e+09 7.197321e+03 6.902584e+02 6.549562e+05 4.757287e+09 91
  193. 492beed5 66355200 7.077888e+09 2.322727e+04 1.128695e+03 2.253045e+06 5.245566e+10 97
  194. ####################
  195. # COMB_1
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 6
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda6_impl0 (Comb1)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 0b0b0ce8 7372800 2.621440e+08 1.063382e+03 9.562944e+01 5.529587e+04 5.927619e+07 52
  223. 4220e23d 29491200 2.097152e+09 7.227464e+03 8.541890e+02 6.287894e+05 4.608031e+09 87
  224. 492beed5 66355200 7.077888e+09 2.322877e+04 9.079114e+02 2.253191e+06 5.241882e+10 97
  225. ####################
  226. # COMB_6
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 3
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda3_impl0 (Comb6)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 0b0b0ce8 7372800 2.621440e+08 1.057961e+03 6.059722e+01 5.289807e+04 5.614771e+07 50
  254. 4220e23d 29491200 2.097152e+09 7.169935e+03 6.166650e+02 5.592549e+05 4.039483e+09 78
  255. 492beed5 66355200 7.077888e+09 2.322622e+04 8.447450e+02 2.090360e+06 4.861539e+10 90
  256. ####################
  257. # COMB_8
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 0
  264. ####################
  265. # DEV_0
  266. # device id
  267. 0
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cpu0_impl0 (Comb8)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 0b0b0ce8 7372800 2.621440e+08 3.132122e+04 3.995607e+03 8.456730e+05 2.691857e+10 27
  285. 4220e23d 29491200 2.097152e+09 2.241875e+05 7.780157e+03 6.053063e+06 1.358656e+12 27
  286. 492beed5 66355200 7.077888e+09 7.222063e+05 7.344712e+03 1.661074e+07 1.199762e+13 23