save_cl_top.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 4af260f6 14678040 0.000000e+00 3.501046e+01 7.466097e+00 2.835847e+04 1.037995e+06 810
  37. fb4b8624 4427800 0.000000e+00 2.773216e+01 6.482940e+00 1.680846e+05 4.916085e+06 6061
  38. f2ff9ae5 34480152 0.000000e+00 5.337509e+01 1.160081e+01 6.591824e+04 3.684596e+06 1235
  39. ####################
  40. # COMB_1
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb1)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 4af260f6 14678040 0.000000e+00 3.362211e+01 7.569501e+00 1.795421e+04 6.342550e+05 534
  68. fb4b8624 4427800 0.000000e+00 3.231969e+01 5.862640e+00 1.877774e+04 6.268602e+05 581
  69. f2ff9ae5 34480152 0.000000e+00 3.995777e+01 9.699452e+00 3.180638e+04 1.345799e+06 796
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 2
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda2_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 4af260f6 14678040 0.000000e+00 3.654429e+01 8.110997e+00 1.710273e+04 6.557958e+05 468
  99. fb4b8624 4427800 0.000000e+00 3.606370e+01 8.402269e+00 2.171034e+04 8.254553e+05 602
  100. f2ff9ae5 34480152 0.000000e+00 3.192218e+01 6.956874e+00 1.695068e+04 5.668019e+05 531
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 1
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda1_impl0 (Comb3)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 4af260f6 14678040 0.000000e+00 3.551068e+01 7.784366e+00 1.278384e+04 4.757777e+05 360
  130. fb4b8624 4427800 0.000000e+00 3.460669e+01 7.284566e+00 1.996806e+04 7.216470e+05 577
  131. f2ff9ae5 34480152 0.000000e+00 3.547098e+01 8.430109e+00 2.805755e+04 1.051443e+06 791
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 4af260f6 14678040 0.000000e+00 3.712899e+01 8.969310e+00 2.030956e+04 7.980787e+05 547
  161. fb4b8624 4427800 0.000000e+00 3.619911e+01 8.162351e+00 2.287784e+04 8.702638e+05 632
  162. f2ff9ae5 34480152 0.000000e+00 3.132201e+01 6.179930e+00 2.584066e+04 8.408892e+05 825