save_cl_top.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 4af260f6 14678040 0.000000e+00 3.246622e+01 6.891153e+00 3.928413e+03 1.332868e+05 121
  37. fb4b8624 4427800 0.000000e+00 1.139753e+01 2.243693e+00 2.644226e+03 3.130556e+04 232
  38. f2ff9ae5 34480152 0.000000e+00 5.591168e+01 1.328211e+01 1.241239e+04 7.331618e+05 222
  39. ####################
  40. # COMB_1
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 4
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda4_impl0 (Comb1)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 4af260f6 14678040 0.000000e+00 2.604823e+01 3.286196e+00 1.130493e+04 2.991603e+05 434
  68. fb4b8624 4427800 0.000000e+00 2.652276e+01 4.354433e+00 7.850738e+03 2.138358e+05 296
  69. f2ff9ae5 34480152 0.000000e+00 2.714414e+01 3.836601e+00 1.555359e+04 4.306232e+05 573
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 1
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda1_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 4af260f6 14678040 0.000000e+00 2.599288e+01 3.808778e+00 1.115095e+04 2.960687e+05 429
  99. fb4b8624 4427800 0.000000e+00 2.539365e+01 2.861737e+00 6.678529e+03 1.717461e+05 263
  100. f2ff9ae5 34480152 0.000000e+00 2.629746e+01 2.517281e+00 1.159718e+04 3.077710e+05 441
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb3)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 4af260f6 14678040 0.000000e+00 2.561750e+01 2.633232e+00 1.155349e+04 2.990988e+05 451
  130. fb4b8624 4427800 0.000000e+00 2.673210e+01 4.378492e+00 1.031859e+04 2.832378e+05 386
  131. f2ff9ae5 34480152 0.000000e+00 2.631930e+01 2.903449e+00 1.339652e+04 3.568781e+05 509
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 6
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda6_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 4af260f6 14678040 0.000000e+00 2.607685e+01 3.121182e+00 7.979517e+03 2.110617e+05 306
  161. fb4b8624 4427800 0.000000e+00 2.621449e+01 3.800716e+00 7.654632e+03 2.048804e+05 292
  162. f2ff9ae5 34480152 0.000000e+00 2.661811e+01 2.706929e+00 1.810031e+04 4.867788e+05 680
  163. ####################
  164. # COMB_5
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 0
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda0_impl0 (Comb5)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 4af260f6 14678040 0.000000e+00 2.759081e+01 5.463486e+00 5.435390e+03 1.558472e+05 197
  192. fb4b8624 4427800 0.000000e+00 2.575898e+01 3.723342e+00 7.779212e+03 2.045713e+05 302
  193. f2ff9ae5 34480152 0.000000e+00 2.684177e+01 3.098778e+00 1.181038e+04 3.212366e+05 440
  194. ####################
  195. # COMB_6
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 3
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda3_impl0 (Comb6)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 4af260f6 14678040 0.000000e+00 2.613306e+01 2.901462e+00 1.100202e+04 2.910606e+05 421
  223. fb4b8624 4427800 0.000000e+00 2.615768e+01 3.461177e+00 7.010257e+03 1.865826e+05 268
  224. f2ff9ae5 34480152 0.000000e+00 2.749333e+01 3.923485e+00 1.492888e+04 4.188033e+05 543
  225. ####################
  226. # COMB_7
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 5
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda5_impl0 (Comb7)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 4af260f6 14678040 0.000000e+00 2.628755e+01 3.829892e+00 1.025215e+04 2.752243e+05 390
  254. fb4b8624 4427800 0.000000e+00 2.540957e+01 3.333356e+00 8.258109e+03 2.134461e+05 325
  255. f2ff9ae5 34480152 0.000000e+00 2.728087e+01 3.903560e+00 1.404965e+04 3.911340e+05 515
  256. ####################
  257. # COMB_8
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 7
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda7_impl0 (Comb8)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 4af260f6 14678040 0.000000e+00 2.705248e+01 4.049710e+00 1.163257e+04 3.217418e+05 430
  285. fb4b8624 4427800 0.000000e+00 2.626990e+01 3.774104e+00 6.908983e+03 1.852444e+05 263
  286. f2ff9ae5 34480152 0.000000e+00 2.670502e+01 3.597311e+00 1.303205e+04 3.543362e+05 488