cl_update.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_1
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 3
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda3_impl0 (Comb1)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 8ec75d42 14753312 0.000000e+00 1.292737e+03 8.111826e+01 1.783977e+06 2.315293e+09 1380
  37. 6d78e48f 4461600 0.000000e+00 7.254397e+02 8.693801e+01 2.717497e+06 1.999693e+09 3746
  38. 49ec0825 34613280 0.000000e+00 2.847204e+03 1.159244e+02 5.255939e+06 1.498954e+10 1846
  39. ####################
  40. # COMB_0
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 0
  47. ####################
  48. # DEV_0
  49. # device id
  50. 0
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cpu0_impl0 (Comb0)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 8ec75d42 14753312 0.000000e+00 2.010356e+04 1.739800e+03 4.201644e+06 8.510064e+10 209
  68. 6d78e48f 4461600 0.000000e+00 6.471465e+03 9.708551e+02 2.344612e+07 1.551456e+11 3623
  69. 49ec0825 34613280 0.000000e+00 4.705100e+04 5.067137e+03 1.383299e+07 6.584049e+11 294
  70. ####################
  71. # COMB_3
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 1
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda1_impl0 (Comb3)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 8ec75d42 14753312 0.000000e+00 1.333639e+03 8.095890e+01 1.871095e+06 2.504561e+09 1403
  99. 6d78e48f 4461600 0.000000e+00 7.466797e+02 9.599725e+01 2.594712e+06 1.969443e+09 3475
  100. 49ec0825 34613280 0.000000e+00 2.914989e+03 1.085303e+02 5.037101e+06 1.470345e+10 1728
  101. ####################
  102. # COMB_4
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 0
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda0_impl0 (Comb4)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 8ec75d42 14753312 0.000000e+00 1.319437e+03 8.470023e+01 1.921100e+06 2.545216e+09 1456
  130. 6d78e48f 4461600 0.000000e+00 7.342135e+02 9.435309e+01 2.608661e+06 1.946944e+09 3553
  131. 49ec0825 34613280 0.000000e+00 2.843027e+03 1.019747e+02 5.080489e+06 1.446255e+10 1787
  132. ####################
  133. # COMB_2
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 2
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda2_impl0 (Comb2)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 8ec75d42 14753312 0.000000e+00 1.324805e+03 7.460278e+01 1.748742e+06 2.324088e+09 1320
  161. 6d78e48f 4461600 0.000000e+00 7.321696e+02 8.668478e+01 2.571380e+06 1.909076e+09 3512
  162. 49ec0825 34613280 0.000000e+00 2.873920e+03 1.173279e+02 5.566783e+06 1.602515e+10 1937