cl_update.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_2
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 1
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda1_impl0 (Comb2)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 8ec75d42 14753312 0.000000e+00 1.774670e+03 3.622348e+02 1.348749e+06 2.493306e+09 760
  37. 6d78e48f 4461600 0.000000e+00 1.036351e+03 9.390524e+01 2.839601e+05 2.966985e+08 274
  38. 49ec0825 34613280 0.000000e+00 4.962997e+03 6.650844e+02 5.096998e+06 2.575067e+10 1027
  39. ####################
  40. # COMB_3
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 2
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda2_impl0 (Comb3)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 8ec75d42 14753312 0.000000e+00 1.813689e+03 3.729019e+02 1.331248e+06 2.516537e+09 734
  68. 6d78e48f 4461600 0.000000e+00 1.023951e+03 1.005326e+02 3.553110e+05 3.673281e+08 347
  69. 49ec0825 34613280 0.000000e+00 5.017264e+03 7.095917e+02 4.365019e+06 2.233852e+10 870
  70. ####################
  71. # COMB_0
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 0
  78. ####################
  79. # DEV_0
  80. # device id
  81. 0
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cpu0_impl0 (Comb0)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 8ec75d42 14753312 0.000000e+00 4.692078e+04 5.010795e+02 1.501465e+06 7.045793e+10 32
  99. 6d78e48f 4461600 0.000000e+00 1.405585e+04 1.896523e+02 7.590156e+05 1.067055e+10 54
  100. 49ec0825 34613280 0.000000e+00 1.108029e+05 1.348959e+03 3.545692e+06 3.929311e+11 32
  101. ####################
  102. # COMB_8
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 7
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda7_impl0 (Comb8)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 8ec75d42 14753312 0.000000e+00 1.859413e+03 3.366203e+02 1.309027e+06 2.513795e+09 704
  130. 6d78e48f 4461600 0.000000e+00 1.027564e+03 1.046018e+02 3.483442e+05 3.616551e+08 339
  131. 49ec0825 34613280 0.000000e+00 5.060000e+03 7.405627e+02 4.164380e+06 2.152312e+10 823
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 6
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda6_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 8ec75d42 14753312 0.000000e+00 1.862800e+03 3.783314e+02 8.438483e+05 1.636760e+09 453
  161. 6d78e48f 4461600 0.000000e+00 9.567271e+02 3.148502e+01 5.606421e+05 5.369624e+08 586
  162. 49ec0825 34613280 0.000000e+00 4.965851e+03 6.509733e+02 5.810046e+06 2.934763e+10 1170
  163. ####################
  164. # COMB_6
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 3
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda3_impl0 (Comb6)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 8ec75d42 14753312 0.000000e+00 1.889366e+03 3.958521e+02 1.186522e+06 2.340180e+09 628
  192. 6d78e48f 4461600 0.000000e+00 1.028680e+03 8.044529e+01 2.880303e+05 2.981029e+08 280
  193. 49ec0825 34613280 0.000000e+00 5.035634e+03 7.113130e+02 4.899672e+06 2.516526e+10 973
  194. ####################
  195. # COMB_5
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 0
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda0_impl0 (Comb5)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 8ec75d42 14753312 0.000000e+00 1.814024e+03 3.173708e+02 1.186372e+06 2.217980e+09 654
  223. 6d78e48f 4461600 0.000000e+00 1.025445e+03 7.185494e+01 3.466003e+05 3.571646e+08 338
  224. 49ec0825 34613280 0.000000e+00 5.092715e+03 7.051028e+02 3.513973e+06 1.823871e+10 690
  225. ####################
  226. # COMB_1
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 4
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda4_impl0 (Comb1)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 8ec75d42 14753312 0.000000e+00 1.793350e+03 3.531620e+02 1.388053e+06 2.585801e+09 774
  254. 6d78e48f 4461600 0.000000e+00 1.033622e+03 1.055186e+02 3.783058e+05 3.951004e+08 366
  255. 49ec0825 34613280 0.000000e+00 4.986601e+03 7.025210e+02 5.345636e+06 2.718562e+10 1072
  256. ####################
  257. # COMB_7
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 5
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda5_impl0 (Comb7)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. 8ec75d42 14753312 0.000000e+00 1.781570e+03 3.261441e+02 1.501864e+06 2.765346e+09 843
  285. 6d78e48f 4461600 0.000000e+00 1.022184e+03 1.018115e+02 3.751415e+05 3.872679e+08 367
  286. 49ec0825 34613280 0.000000e+00 5.102994e+03 7.050225e+02 4.327339e+06 2.250389e+10 848