chol_model_21.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 7372800 8.856576e+08 4.711469e+04 4.337925e+02 3.203799e+06 1.509588e+11 68
  37. 2c1922b7 819200 3.287040e+07 1.979166e+03 8.798869e+01 6.828124e+05 1.354070e+09 345
  38. d39bff17 3276800 2.625536e+08 1.482664e+04 2.506296e+02 2.298130e+06 3.408328e+10 155
  39. ####################
  40. # COMB_4
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb4)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 7372800 8.856576e+08 6.573848e+03 6.169449e+02 1.360787e+06 9.024393e+09 207
  68. 2c1922b7 819200 3.287040e+07 6.955196e+02 8.976154e+01 1.286711e+05 9.098386e+07 185
  69. d39bff17 3276800 2.625536e+08 2.647434e+03 2.520462e+02 4.685958e+05 1.251821e+09 177
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 3
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda3_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 7372800 8.856576e+08 6.555664e+03 6.950469e+02 1.252132e+06 8.300825e+09 191
  99. 2c1922b7 819200 3.287040e+07 6.812499e+02 8.342802e+01 1.273937e+05 8.808853e+07 187
  100. d39bff17 3276800 2.625536e+08 2.596800e+03 1.668067e+02 5.894736e+05 1.537061e+09 227
  101. ####################
  102. # COMB_3
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb3)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 7372800 8.856576e+08 6.446442e+03 5.413553e+02 1.276395e+06 8.286236e+09 198
  130. 2c1922b7 819200 3.287040e+07 6.941204e+02 8.002896e+01 1.277182e+05 8.983023e+07 184
  131. d39bff17 3276800 2.625536e+08 2.630763e+03 2.300111e+02 4.603835e+05 1.220418e+09 175
  132. ####################
  133. # COMB_1
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb1)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 7372800 8.856576e+08 6.554622e+03 7.028631e+02 1.238824e+06 8.213390e+09 189
  161. 2c1922b7 819200 3.287040e+07 6.905951e+02 7.284704e+01 1.353566e+05 9.451674e+07 196
  162. d39bff17 3276800 2.625536e+08 2.623425e+03 2.211699e+02 4.905805e+05 1.296149e+09 187
  163. ####################
  164. # COMB_7
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 4
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda4_impl0 (Comb7)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. ff82dda0 7372800 8.856576e+08 6.504271e+03 6.367049e+02 9.951534e+05 6.534773e+09 153
  192. 2c1922b7 819200 3.287040e+07 7.029111e+02 9.289767e+01 7.169693e+04 5.127683e+07 102
  193. d39bff17 3276800 2.625536e+08 2.684586e+03 3.481310e+02 4.080571e+05 1.113886e+09 152
  194. ####################
  195. # COMB_8
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 5
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda5_impl0 (Comb8)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. ff82dda0 7372800 8.856576e+08 6.618862e+03 8.843940e+02 8.405955e+05 5.663119e+09 127
  223. 2c1922b7 819200 3.287040e+07 7.079333e+02 9.356613e+01 6.796160e+04 4.895273e+07 96
  224. d39bff17 3276800 2.625536e+08 2.800887e+03 4.371231e+02 3.221020e+05 9.241450e+08 115
  225. ####################
  226. # COMB_5
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 6
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda6_impl0 (Comb5)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. ff82dda0 7372800 8.856576e+08 6.576395e+03 7.489644e+02 8.878133e+05 5.914339e+09 135
  254. 2c1922b7 819200 3.287040e+07 7.050156e+02 1.025857e+02 8.037177e+04 5.786307e+07 114
  255. d39bff17 3276800 2.625536e+08 2.645162e+03 2.750078e+02 4.205807e+05 1.124529e+09 159
  256. ####################
  257. # COMB_6
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 7
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda7_impl0 (Comb6)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. ff82dda0 7372800 8.856576e+08 6.544427e+03 6.576164e+02 9.358531e+05 6.186464e+09 143
  285. 2c1922b7 819200 3.287040e+07 7.150712e+02 1.054194e+02 8.223319e+04 6.008061e+07 115
  286. d39bff17 3276800 2.625536e+08 2.613530e+03 2.505172e+02 3.972565e+05 1.047781e+09 152