chol_model_11.idgraf 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 617e5fe6 3686400 2.953730e+08 2.069576e+04 7.440388e+01 4.346110e+05 8.994720e+09 21
  37. cea37d6d 409600 1.097392e+07 1.068290e+03 2.074934e+01 3.098041e+04 3.310855e+07 29
  38. afdd228b 1638400 8.758624e+07 6.632886e+03 6.634864e+01 1.392906e+05 9.239911e+08 21
  39. ####################
  40. # COMB_6
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 7
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda7_impl0 (Comb6)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 617e5fe6 3686400 2.953730e+08 5.998499e+04 6.600211e+03 5.998499e+05 3.641761e+10 10
  68. cea37d6d 409600 1.097392e+07 1.500406e+04 5.740284e+02 1.500406e+05 2.254514e+09 10
  69. afdd228b 1638400 8.758624e+07 3.368249e+04 5.947857e+03 3.368249e+05 1.169887e+10 10
  70. ####################
  71. # COMB_8
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 5
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda5_impl0 (Comb8)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 617e5fe6 3686400 2.953730e+08 5.745646e+04 7.363450e+03 5.745646e+05 3.355466e+10 10
  99. cea37d6d 409600 1.097392e+07 1.559370e+04 1.137871e+03 1.559370e+05 2.444583e+09 10
  100. afdd228b 1638400 8.758624e+07 3.216379e+04 4.954206e+03 3.216379e+05 1.059054e+10 10
  101. ####################
  102. # COMB_5
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 6
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda6_impl0 (Comb5)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 617e5fe6 3686400 2.953730e+08 5.761859e+04 8.603827e+03 5.761859e+05 3.393928e+10 10
  130. cea37d6d 409600 1.097392e+07 1.498399e+04 7.885417e+02 1.498399e+05 2.251416e+09 10
  131. afdd228b 1638400 8.758624e+07 3.033086e+04 2.968298e+03 3.033086e+05 9.287718e+09 10
  132. ####################
  133. # COMB_7
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 4
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda4_impl0 (Comb7)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 617e5fe6 3686400 2.953730e+08 5.207197e+04 2.780602e+03 5.207197e+05 2.719222e+10 10
  161. cea37d6d 409600 1.097392e+07 1.609271e+04 2.681035e+03 1.609271e+05 2.661633e+09 10
  162. afdd228b 1638400 8.758624e+07 3.107603e+04 1.620445e+03 3.107603e+05 9.683455e+09 10
  163. ####################
  164. # COMB_1
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 0
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda0_impl0 (Comb1)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. 617e5fe6 3686400 2.953730e+08 5.062446e+04 2.429137e+03 5.062446e+05 2.568736e+10 10
  192. cea37d6d 409600 1.097392e+07 1.506158e+04 8.561331e+02 1.506158e+05 2.275840e+09 10
  193. afdd228b 1638400 8.758624e+07 3.034398e+04 4.027845e+03 3.034398e+05 9.369809e+09 10
  194. ####################
  195. # COMB_4
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 1
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda1_impl0 (Comb4)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. 617e5fe6 3686400 2.953730e+08 5.174953e+04 6.183695e+03 5.174953e+05 2.716252e+10 10
  223. cea37d6d 409600 1.097392e+07 1.518996e+04 9.403764e+02 1.518996e+05 2.316193e+09 10
  224. afdd228b 1638400 8.758624e+07 3.100983e+04 5.124047e+03 3.100983e+05 9.878653e+09 10
  225. ####################
  226. # COMB_2
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 3
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda3_impl0 (Comb2)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. 617e5fe6 3686400 2.953730e+08 5.475211e+04 6.512121e+03 5.475211e+05 3.040202e+10 10
  254. cea37d6d 409600 1.097392e+07 1.504708e+04 5.064339e+02 1.504708e+05 2.266711e+09 10
  255. afdd228b 1638400 8.758624e+07 2.918927e+04 4.035680e+03 2.918927e+05 8.683004e+09 10
  256. ####################
  257. # COMB_3
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 2
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda2_impl0 (Comb3)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. cea37d6d 409600 1.097392e+07 1.467875e+04 2.659893e+02 1.467875e+05 2.155366e+09 10
  285. afdd228b 1638400 8.758624e+07 3.186232e+04 5.396938e+03 3.186232e+05 1.044334e+10 10
  286. 617e5fe6 3686400 2.953730e+08 5.896762e+04 1.233845e+04 5.896762e+05 3.629418e+10 10