starpu_slu_lu_model_22.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 24c84a50 11059200 0.000000e+00 3.517390e+04 7.045528e+03 6.925741e+07 2.533794e+12 1969
  37. d46431bb 1228800 0.000000e+00 1.613402e+03 3.115535e+02 8.438094e+06 1.412169e+10 5230
  38. f0ac7beb 4915200 0.000000e+00 1.087142e+04 2.109400e+03 2.505863e+07 2.826792e+11 2305
  39. ####################
  40. # COMB_3
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 0
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda0_impl0 (Comb3)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 24c84a50 11059200 0.000000e+00 7.851775e+02 4.684799e+01 4.315336e+06 3.400367e+09 5496
  68. d46431bb 1228800 0.000000e+00 6.142508e+01 1.012391e+01 4.393736e+05 2.772170e+07 7153
  69. f0ac7beb 4915200 0.000000e+00 2.657700e+02 2.996380e+01 1.356225e+06 3.650255e+08 5103
  70. ####################
  71. # COMB_2
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 2
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda2_impl0 (Comb2)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 24c84a50 11059200 0.000000e+00 7.926860e+02 4.760061e+01 4.363736e+06 3.471546e+09 5505
  99. d46431bb 1228800 0.000000e+00 6.592485e+01 1.426453e+01 1.071279e+05 7.393038e+06 1625
  100. f0ac7beb 4915200 0.000000e+00 2.693001e+02 2.710216e+01 1.308798e+06 3.560293e+08 4860
  101. ####################
  102. # COMB_1
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 1
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda1_impl0 (Comb1)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 24c84a50 11059200 0.000000e+00 7.922324e+02 5.091772e+01 4.156844e+06 3.306790e+09 5247
  130. d46431bb 1228800 0.000000e+00 6.317490e+01 1.087216e+01 2.866877e+05 1.864788e+07 4538
  131. f0ac7beb 4915200 0.000000e+00 2.686331e+02 2.912062e+01 1.401996e+06 3.810483e+08 5219
  132. ####################
  133. # COMB_0
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 3
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda3_impl0 (Comb0)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 24c84a50 11059200 0.000000e+00 7.867204e+02 4.699968e+01 4.148377e+06 3.275261e+09 5273
  161. d46431bb 1228800 0.000000e+00 5.975719e+01 9.345113e+00 4.033610e+05 2.469321e+07 6750
  162. f0ac7beb 4915200 0.000000e+00 2.642224e+02 2.666799e+01 1.450317e+06 3.871098e+08 5489