starpu_slu_lu_model_12.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 7372800 0.000000e+00 1.726784e+04 3.264426e+03 3.021872e+06 5.404608e+10 175
  37. 2c1922b7 819200 0.000000e+00 4.245334e+03 7.020174e+02 6.368000e+04 2.777353e+08 15
  38. d39bff17 3276800 0.000000e+00 5.106660e+03 6.848530e+02 2.134584e+06 1.109665e+10 418
  39. ####################
  40. # COMB_0
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb0)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 7372800 0.000000e+00 2.106719e+03 2.638200e+02 5.646006e+05 1.208108e+09 268
  68. 2c1922b7 819200 0.000000e+00 4.901281e+02 6.729653e+01 6.616730e+04 3.304185e+07 135
  69. d39bff17 3276800 0.000000e+00 1.216432e+03 1.410794e+02 1.934127e+05 2.384382e+08 159
  70. ####################
  71. # COMB_1
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 1
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda1_impl0 (Comb1)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 7372800 0.000000e+00 2.138085e+03 2.696288e+02 6.371492e+05 1.383944e+09 298
  99. 2c1922b7 819200 0.000000e+00 4.968224e+02 7.860110e+01 5.415364e+04 2.757816e+07 109
  100. d39bff17 3276800 0.000000e+00 1.199302e+03 1.658297e+02 1.774966e+05 2.169419e+08 148
  101. ####################
  102. # COMB_2
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb2)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 7372800 0.000000e+00 2.196957e+03 3.265420e+02 4.349975e+05 9.767837e+08 198
  130. 2c1922b7 819200 0.000000e+00 8.901347e+01 1.918734e+01 2.412265e+04 2.247011e+06 271
  131. d39bff17 3276800 0.000000e+00 1.148300e+03 2.163448e+02 2.021009e+05 2.403102e+08 176
  132. ####################
  133. # COMB_3
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb3)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 7372800 0.000000e+00 2.164310e+03 2.607466e+02 4.869698e+05 1.069251e+09 225
  161. 2c1922b7 819200 0.000000e+00 4.930666e+02 7.623523e+01 7.642532e+04 3.858360e+07 155
  162. d39bff17 3276800 0.000000e+00 1.203544e+03 1.679024e+02 2.286733e+05 2.805746e+08 190