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starpu-max
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StreamFMA_MAX5C_DFE_SIM
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Manager_StreamFMA_Original.mxg

Manager_StreamFMA_Original.mxg 9.1 KB
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  1. <?xml version="1.0" encoding="UTF-8" ?>
    2. 

  2. <ManagerGraph version="2018.3.1" design_name="Manager_StreamFMA" compilation_phase="Original" hardwareBuild="false">
    3. 

  3. 	<Node id="45" instanceName="addrgen_cmd_MemoryControllerPro0_inBT2" type="McpAddressGenerator">
    4. 

  4. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    5. 

  5. 			<Stream name="Stream_47" sink="22" />
    6. 

  6. 		</Output>
    7. 

  7. 	</Node>
    8. 

  8. 	<Node id="61" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT2" type="McpAddressGenerator">
    9. 

  9. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    10. 

  10. 			<Stream name="Stream_63" sink="22" />
    11. 

  11. 		</Output>
    12. 

  12. 	</Node>
    13. 

  13. 	<Node id="5" instanceName="inBT1" type="Input">
    14. 

  14. 		<Output clock="PCIE" name="inBT1" type="PUSH 2" width="128">
    15. 

  15. 			<Stream name="Stream_6" sink="0" />
    16. 

  16. 		</Output>
    17. 

  17. 	</Node>
    18. 

  18. 	<Node id="49" instanceName="addrgen_cmd_MemoryControllerPro0_inAT3" type="McpAddressGenerator">
    19. 

  19. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    20. 

  20. 			<Stream name="Stream_51" sink="22" />
    21. 

  21. 		</Output>
    22. 

  22. 	</Node>
    23. 

  23. 	<Node id="2" instanceName="inAT1" type="Input">
    24. 

  24. 		<Output clock="PCIE" name="inAT1" type="PUSH 2" width="128">
    25. 

  25. 			<Stream name="Stream_3" sink="0" />
    26. 

  26. 		</Output>
    27. 

  27. 	</Node>
    28. 

  28. 	<Node id="53" instanceName="addrgen_cmd_MemoryControllerPro0_inBT3" type="McpAddressGenerator">
    29. 

  29. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    30. 

  30. 			<Stream name="Stream_55" sink="22" />
    31. 

  31. 		</Output>
    32. 

  32. 	</Node>
    33. 

  33. 	<Node id="57" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT1" type="McpAddressGenerator">
    34. 

  34. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    35. 

  35. 			<Stream name="Stream_59" sink="22" />
    36. 

  36. 		</Output>
    37. 

  37. 	</Node>
    38. 

  38. 	<Node id="41" instanceName="addrgen_cmd_MemoryControllerPro0_inAT2" type="McpAddressGenerator">
    39. 

  39. 		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
    40. 

  40. 			<Stream name="Stream_43" sink="22" />
    41. 

  41. 		</Output>
    42. 

  42. 	</Node>
    43. 

  43. 	<Node id="65" instanceName="Stream_34_pipeline_4" type="Pipeline">
    44. 

  44. 		<Input clock="DDR_CLK_a" name="input" type="PUSH 1" width="-1">
    45. 

  45. 			<Stream name="Stream_66" source="31" />
    46. 

  46. 		</Input>
    47. 

  47. 		<Output clock="DDR_CLK_a" name="output" type="PUSH 9" width="-1">
    48. 

  48. 			<Stream name="Stream_67" sink="22" />
    49. 

  49. 		</Output>
    50. 

  50. 	</Node>
    51. 

  51. 	<Node id="77" instanceName="Stream_28_pipeline_4" type="Pipeline">
    52. 

  52. 		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
    53. 

  53. 			<Stream name="Stream_78" source="22" />
    54. 

  54. 		</Input>
    55. 

  55. 		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
    56. 

  56. 			<Stream name="Stream_79" sink="26" />
    57. 

  57. 		</Output>
    58. 

  58. 	</Node>
    59. 

  59. 	<Node id="26" instanceName="MemoryControllerInterface_b" type="Max5Mci">
    60. 

  60. 		<Input clock="DDR_CLK_b" name="cmd_stream_maxj" type="PULL el=1" width="544">
    61. 

  61. 			<Stream name="Stream_80" source="77" />
    62. 

  62. 		</Input>
    63. 

  63. 		<Output clock="DDR_CLK_b" name="read_stream_maxj" type="PUSH 1" width="512">
    64. 

  64. 			<Stream name="Stream_29" sink="69" />
    65. 

  65. 		</Output>
    66. 

  66. 	</Node>
    67. 

  67. 	<Node id="69" instanceName="Stream_29_pipeline_4" type="Pipeline">
    68. 

  68. 		<Input clock="DDR_CLK_b" name="input" type="PUSH 1" width="-1">
    69. 

  69. 			<Stream name="Stream_70" source="26" />
    70. 

  70. 		</Input>
    71. 

  71. 		<Output clock="DDR_CLK_b" name="output" type="PUSH 9" width="-1">
    72. 

  72. 			<Stream name="Stream_71" sink="22" />
    73. 

  73. 		</Output>
    74. 

  74. 	</Node>
    75. 

  75. 	<Node id="31" instanceName="MemoryControllerInterface_a" type="Max5Mci">
    76. 

  76. 		<Input clock="DDR_CLK_a" name="cmd_stream_maxj" type="PULL el=1" width="544">
    77. 

  77. 			<Stream name="Stream_84" source="81" />
    78. 

  78. 		</Input>
    79. 

  79. 		<Output clock="DDR_CLK_a" name="read_stream_maxj" type="PUSH 1" width="512">
    80. 

  80. 			<Stream name="Stream_34" sink="65" />
    81. 

  81. 		</Output>
    82. 

  82. 	</Node>
    83. 

  83. 	<Node id="81" instanceName="Stream_33_pipeline_4" type="Pipeline">
    84. 

  84. 		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
    85. 

  85. 			<Stream name="Stream_82" source="22" />
    86. 

  86. 		</Input>
    87. 

  87. 		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
    88. 

  88. 			<Stream name="Stream_83" sink="31" />
    89. 

  89. 		</Output>
    90. 

  90. 	</Node>
    91. 

  91. 	<Node id="22" instanceName="MemoryControllerPro0" type="MemoryControllerPro">
    92. 

  92. 		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_a" type="PULL el=1 ael=3" width="512">
    93. 

  93. 			<Stream name="Stream_68" source="65" />
    94. 

  94. 		</Input>
    95. 

  95. 		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_b" type="PULL el=1 ael=3" width="512">
    96. 

  96. 			<Stream name="Stream_72" source="69" />
    97. 

  97. 		</Input>
    98. 

  98. 		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_c" type="PULL el=1 ael=3" width="512">
    99. 

  99. 			<Stream name="Stream_76" source="73" />
    100. 

  100. 		</Input>
    101. 

  101. 		<Input clock="MemoryControllerPro0_clk" name="read_command_0" type="PUSH 8" width="64">
    102. 

  102. 			<Stream name="Stream_42" source="41" />
    103. 

  103. 		</Input>
    104. 

  104. 		<Input clock="MemoryControllerPro0_clk" name="read_command_1" type="PUSH 8" width="64">
    105. 

  105. 			<Stream name="Stream_46" source="45" />
    106. 

  106. 		</Input>
    107. 

  107. 		<Input clock="MemoryControllerPro0_clk" name="read_command_2" type="PUSH 8" width="64">
    108. 

  108. 			<Stream name="Stream_50" source="49" />
    109. 

  109. 		</Input>
    110. 

  110. 		<Input clock="MemoryControllerPro0_clk" name="read_command_3" type="PUSH 8" width="64">
    111. 

  111. 			<Stream name="Stream_54" source="53" />
    112. 

  112. 		</Input>
    113. 

  113. 		<Input clock="STREAM" name="write_0" type="PUSH 8" width="1536">
    114. 

  114. 			<Stream name="Stream_60" source="0" />
    115. 

  115. 		</Input>
    116. 

  116. 		<Input clock="STREAM" name="write_1" type="PUSH 8" width="1536">
    117. 

  117. 			<Stream name="Stream_64" source="0" />
    118. 

  118. 		</Input>
    119. 

  119. 		<Input clock="MemoryControllerPro0_clk" name="write_command_0" type="PUSH 8" width="64">
    120. 

  120. 			<Stream name="Stream_58" source="57" />
    121. 

  121. 		</Input>
    122. 

  122. 		<Input clock="MemoryControllerPro0_clk" name="write_command_1" type="PUSH 8" width="64">
    123. 

  123. 			<Stream name="Stream_62" source="61" />
    124. 

  124. 		</Input>
    125. 

  125. 		<Output clock="STREAM" name="read_0" type="PULL el=1 ael=8" width="1536">
    126. 

  126. 			<Stream name="Stream_44" sink="0" />
    127. 

  127. 		</Output>
    128. 

  128. 		<Output clock="STREAM" name="read_1" type="PULL el=1 ael=8" width="1536">
    129. 

  129. 			<Stream name="Stream_48" sink="0" />
    130. 

  130. 		</Output>
    131. 

  131. 		<Output clock="STREAM" name="read_2" type="PULL el=1 ael=8" width="1536">
    132. 

  132. 			<Stream name="Stream_52" sink="0" />
    133. 

  133. 		</Output>
    134. 

  134. 		<Output clock="STREAM" name="read_3" type="PULL el=1 ael=8" width="1536">
    135. 

  135. 			<Stream name="Stream_56" sink="0" />
    136. 

  136. 		</Output>
    137. 

  137. 		<Output clock="MemoryControllerPro0_clk" name="Tag_Out" type="PUSH 1" width="1">
    138. 

  138. 			<Stream name="Stream_25" sink="23" />
    139. 

  139. 		</Output>
    140. 

  140. 		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_a" type="PUSH 3" width="544">
    141. 

  141. 			<Stream name="Stream_33" sink="81" />
    142. 

  142. 		</Output>
    143. 

  143. 		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_b" type="PUSH 3" width="544">
    144. 

  144. 			<Stream name="Stream_28" sink="77" />
    145. 

  145. 		</Output>
    146. 

  146. 		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_c" type="PUSH 3" width="544">
    147. 

  147. 			<Stream name="Stream_38" sink="85" />
    148. 

  148. 		</Output>
    149. 

  149. 	</Node>
    150. 

  150. 	<Node id="0" instanceName="StreamFMAKernel" type="Kernel">
    151. 

  151. 		<PxgFile phase="original">StreamFMA-StreamFMAKernel-original.pxg</PxgFile>
    152. 

  152. 		<Input clock="STREAM" name="inAT1" type="PULL el=1 ael=2" width="32">
    153. 

  153. 			<Stream name="Stream_1" source="2" />
    154. 

  154. 		</Input>
    155. 

  155. 		<Input clock="STREAM" name="inBT1" type="PULL el=1 ael=2" width="32">
    156. 

  156. 			<Stream name="Stream_4" source="5" />
    157. 

  157. 		</Input>
    158. 

  158. 		<Input clock="STREAM" name="inAT2" type="PULL el=1 ael=2" width="32">
    159. 

  159. 			<Stream name="Stream_8" source="22" />
    160. 

  160. 		</Input>
    161. 

  161. 		<Input clock="STREAM" name="inBT2" type="PULL el=1 ael=2" width="32">
    162. 

  162. 			<Stream name="Stream_10" source="22" />
    163. 

  163. 		</Input>
    164. 

  164. 		<Input clock="STREAM" name="inAT3" type="PULL el=1 ael=2" width="32">
    165. 

  165. 			<Stream name="Stream_12" source="22" />
    166. 

  166. 		</Input>
    167. 

  167. 		<Input clock="STREAM" name="inBT3" type="PULL el=1 ael=2" width="32">
    168. 

  168. 			<Stream name="Stream_14" source="22" />
    169. 

  169. 		</Input>
    170. 

  170. 		<Output clock="STREAM" name="oDataT1" type="PUSH 5" width="32">
    171. 

  171. 			<Stream name="Stream_16" sink="22" />
    172. 

  172. 		</Output>
    173. 

  173. 		<Output clock="STREAM" name="oDataT2" type="PUSH 5" width="32">
    174. 

  174. 			<Stream name="Stream_18" sink="22" />
    175. 

  175. 		</Output>
    176. 

  176. 		<Output clock="STREAM" name="oDataT3" type="PUSH 5" width="32">
    177. 

  177. 			<Stream name="Stream_21" sink="19" />
    178. 

  178. 		</Output>
    179. 

  179. 	</Node>
    180. 

  180. 	<Node id="23" instanceName="MemoryControllerPro0_IntSource" type="_A">
    181. 

  181. 		<Input clock="clk" name="Tag_In" type="PUSH 1" width="1">
    182. 

  182. 			<Stream name="Stream_24" source="22" />
    183. 

  183. 		</Input>
    184. 

  184. 	</Node>
    185. 

  185. 	<Node id="85" instanceName="Stream_38_pipeline_4" type="Pipeline">
    186. 

  186. 		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
    187. 

  187. 			<Stream name="Stream_86" source="22" />
    188. 

  188. 		</Input>
    189. 

  189. 		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
    190. 

  190. 			<Stream name="Stream_87" sink="36" />
    191. 

  191. 		</Output>
    192. 

  192. 	</Node>
    193. 

  193. 	<Node id="19" instanceName="oDataT3" type="Output">
    194. 

  194. 		<Input clock="PCIE" name="oDataT3" type="PUSH 1" width="128">
    195. 

  195. 			<Stream name="Stream_20" source="0" />
    196. 

  196. 		</Input>
    197. 

  197. 	</Node>
    198. 

  198. 	<Node id="36" instanceName="MemoryControllerInterface_c" type="Max5Mci">
    199. 

  199. 		<Input clock="DDR_CLK_c" name="cmd_stream_maxj" type="PULL el=1" width="544">
    200. 

  200. 			<Stream name="Stream_88" source="85" />
    201. 

  201. 		</Input>
    202. 

  202. 		<Output clock="DDR_CLK_c" name="read_stream_maxj" type="PUSH 1" width="512">
    203. 

  203. 			<Stream name="Stream_39" sink="73" />
    204. 

  204. 		</Output>
    205. 

  205. 	</Node>
    206. 

  206. 	<Node id="73" instanceName="Stream_39_pipeline_4" type="Pipeline">
    207. 

  207. 		<Input clock="DDR_CLK_c" name="input" type="PUSH 1" width="-1">
    208. 

  208. 			<Stream name="Stream_74" source="36" />
    209. 

  209. 		</Input>
    210. 

  210. 		<Output clock="DDR_CLK_c" name="output" type="PUSH 9" width="-1">
    211. 

  211. 			<Stream name="Stream_75" sink="22" />
    212. 

  212. 		</Output>
    213. 

  213. 	</Node>
    214. 

  214. </ManagerGraph>
    215. 

  215.