starpu-max/tests/perfmodels/StreamFMA.max

#ifdef MAXCOMPILER_VERSION_INFO
#define MAXCOMPILER_VERSION_INFO_PRESENT 1
#define MAXFILE_MAXCOMPILER_VERSION_YEAR         2018
#define MAXFILE_MAXCOMPILER_VERSION_NUM          3
#define MAXFILE_MAXCOMPILER_VERSION_POINT        1
#define MAXFILE_MAXCOMPILER_VERSION_PATCH        ""
#define MAXFILE_MAXCOMPILER_VERSION_REV          "b189b8e"
#define MAXFILE_MAXCOMPILER_VERSION_RELEASE_DATE "2019-01-09"
#define MAXFILE_MAXCOMPILER_VERSION_RELEASE_MODE true
#endif

#ifdef MAXFILE_BUILD_INFO
#define MAXFILE_BUILD_INFO_PRESENT 1
#define MAXFILE_BUILD_NAME "StreamFMA"
#define MAXFILE_BUILD_DIR  "/mnt/beegfs/home/jusers/makni1/jumax/makni2/starpu.git/tests/./StreamFMA_MAX5C_DFE_SIM"
#define MAXFILE_BUILD_DATE  20200128
#define MAXFILE_BUILD_REV   1
#endif

#ifdef PARAM
#define PARAM_PRESENT 1
PARAM(DYNAMIC_CLOCKS_ENABLED, 0)
PARAM(MemCtrlPro_TotalNumStreams0, 6)
PARAM(MemCtrlPro_NumRdStreams0, 4)
PARAM(MemCtrlPro_NumWrStreams0, 2)
PARAM(MemCtrlPro_DDRType0, 4)
PARAM(MemCtrlPro_BurstSizeInBytes0, 192)
PARAM(MemCtrlPro_MainFIFODepth0, 512)
PARAM(APP_ID, 0)
PARAM(REV_ID, 0)
PARAM(CHAIN_LENGTH, 160)
PARAM(IS_SIMULATION, 1)
PARAM(MEC_SUPPORTED, 1)
PARAM(PCIE_SLAVE_STREAMING, 0)
PARAM(PCIE_ALIGNMENT, 16)
PARAM(NUM_IFPGA_LINKS, 0)
#endif

#ifdef STRING_PARAM
#define STRING_PARAM_PRESENT 1
STRING_PARAM(BOARD_MODEL, "MAX5_LIMA")
#endif



#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StateMachineManagerBlock_impl_MemoryControllerPro0.h"
#endif

#ifdef INCLUDE_GENERATED_CPP_HEADERS
#include "StreamFMAKernel.h"
#endif



#ifdef ENGINE_PARAMETERS
#define ENGINE_PARAMETERS_PRESENT 1
ENGINE_PARAMETERS(DFEModel, DFEMODEL, MAIA)
ENGINE_PARAMETERS(maxFileName, STRING, "StreamFMA")
ENGINE_PARAMETERS(target, ENUM, DFE_SIM)
ENGINE_PARAMETERS(enableMPCX, BOOL, false)
ENGINE_PARAMETERS(MPPRStartCT, INT, 1)
ENGINE_PARAMETERS(MPPREndCT, INT, 1)
ENGINE_PARAMETERS(MPPRThreads, INT, 1)
ENGINE_PARAMETERS(MPPRRetryThreshold, INT, 0)
#endif

#ifdef MANAGER_NODE
#define MANAGER_NODE_PRESENT 1
MANAGER_NODE(StreamFMAKernel, Kernel)
MANAGER_NODE(inAT1, PCIe_From_Host)
MANAGER_NODE(inBT1, PCIe_From_Host)
MANAGER_NODE(oDataT3, PCIe_To_Host)
MANAGER_NODE(MemoryControllerPro0, ManagerStateMachine_MemoryControllerPro0)
MANAGER_NODE(MemoryControllerPro0_IntSource, MemoryInterruptSource)
MANAGER_NODE(MemoryControllerInterface_b, MemoryControllerInterface_b)
MANAGER_NODE(MemoryControllerInterface_a, MemoryControllerInterface_a)
MANAGER_NODE(MemoryControllerInterface_c, MemoryControllerInterface_c)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_inAT2, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_inBT2, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_inAT3, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_inBT3, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_oDataT1, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1)
MANAGER_NODE(addrgen_cmd_MemoryControllerPro0_oDataT2, ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2)
MANAGER_NODE(Stream_34_pipeline_4, Stream_34_pipeline)
MANAGER_NODE(Stream_29_pipeline_4, Stream_29_pipeline)
MANAGER_NODE(Stream_39_pipeline_4, Stream_39_pipeline)
MANAGER_NODE(Stream_28_pipeline_4, Stream_28_pipeline)
MANAGER_NODE(Stream_33_pipeline_4, Stream_33_pipeline)
MANAGER_NODE(Stream_38_pipeline_4, Stream_38_pipeline)
MANAGER_NODE(Stream_60, DualAspectReg)
MANAGER_NODE(Stream_64, DualAspectReg)
MANAGER_NODE(Stream_1, DualAspectMux)
MANAGER_NODE(Stream_4, DualAspectMux)
MANAGER_NODE(Stream_8, DualAspectMux)
MANAGER_NODE(Stream_10, DualAspectMux)
MANAGER_NODE(Stream_12, DualAspectMux)
MANAGER_NODE(Stream_14, DualAspectMux)
MANAGER_NODE(Stream_20, DualAspectReg)
MANAGER_NODE(Stream_92, StreamPullPushAdapter)
MANAGER_NODE(Stream_96, StreamPullPushAdapter)
MANAGER_NODE(Stream_124, StreamPullPushAdapter)
MANAGER_NODE(Stream_98, Fifo)
MANAGER_NODE(Stream_102, Fifo)
MANAGER_NODE(Stream_94, Fifo)
MANAGER_NODE(Stream_80, Fifo)
MANAGER_NODE(Stream_84, Fifo)
MANAGER_NODE(Stream_90, Fifo)
MANAGER_NODE(Stream_68, Fifo)
MANAGER_NODE(Stream_72, Fifo)
MANAGER_NODE(Stream_76, Fifo)
MANAGER_NODE(Stream_42, Fifo)
MANAGER_NODE(Stream_46, Fifo)
MANAGER_NODE(Stream_50, Fifo)
MANAGER_NODE(Stream_54, Fifo)
MANAGER_NODE(Stream_58, Fifo)
MANAGER_NODE(Stream_62, Fifo)
MANAGER_NODE(Stream_100, Fifo)
MANAGER_NODE(Stream_104, Fifo)
MANAGER_NODE(Stream_108, Fifo)
MANAGER_NODE(Stream_112, Fifo)
MANAGER_NODE(Stream_116, Fifo)
MANAGER_NODE(Stream_120, Fifo)
MANAGER_NODE(Stream_88, Fifo)
MANAGER_NODE(Stream_122, Fifo)
#endif

#ifdef MANAGER_NODE_IO
#define MANAGER_NODE_IO_PRESENT 1
MANAGER_NODE_IO(StreamFMAKernel, inAT1, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, inBT1, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, inAT2, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, inBT2, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, inAT3, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, inBT3, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(StreamFMAKernel, oDataT1, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(StreamFMAKernel, oDataT2, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(StreamFMAKernel, oDataT3, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(inAT1, inAT1, OUT, PCIE, 128, PUSH)
MANAGER_NODE_IO(inBT1, inBT1, OUT, PCIE, 128, PUSH)
MANAGER_NODE_IO(oDataT3, oDataT3, IN, PCIE, 128, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, read_stream_maxj_a, IN, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_stream_maxj_b, IN, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_stream_maxj_c, IN, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_command_0, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, read_command_1, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, read_command_2, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, read_command_3, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, write_0, IN, STREAM, 1536, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, write_1, IN, STREAM, 1536, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, write_command_0, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, write_command_1, IN, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, read_0, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_1, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_2, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, read_3, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(MemoryControllerPro0, Tag_Out, OUT, MemoryControllerPro0_clk, 1, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, cmd_stream_maxj_a, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, cmd_stream_maxj_b, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0, cmd_stream_maxj_c, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(MemoryControllerPro0_IntSource, Tag_In, IN, MemoryControllerPro0_clk, 1, PUSH)
MANAGER_NODE_IO(MemoryControllerInterface_b, cmd_stream_maxj, IN, DDR_CLK_b, 544, PULL)
MANAGER_NODE_IO(MemoryControllerInterface_b, read_stream_maxj, OUT, DDR_CLK_b, 512, PUSH)
MANAGER_NODE_IO(MemoryControllerInterface_a, cmd_stream_maxj, IN, DDR_CLK_a, 544, PULL)
MANAGER_NODE_IO(MemoryControllerInterface_a, read_stream_maxj, OUT, DDR_CLK_a, 512, PUSH)
MANAGER_NODE_IO(MemoryControllerInterface_c, cmd_stream_maxj, IN, DDR_CLK_c, 544, PULL)
MANAGER_NODE_IO(MemoryControllerInterface_c, read_stream_maxj, OUT, DDR_CLK_c, 512, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_inAT2, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_inBT2, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_inAT3, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_inBT3, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_oDataT1, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(addrgen_cmd_MemoryControllerPro0_oDataT2, cgen_out_0, OUT, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_34_pipeline_4, input, IN, DDR_CLK_a, 512, PUSH)
MANAGER_NODE_IO(Stream_34_pipeline_4, output, OUT, DDR_CLK_a, 512, PUSH)
MANAGER_NODE_IO(Stream_29_pipeline_4, input, IN, DDR_CLK_b, 512, PUSH)
MANAGER_NODE_IO(Stream_29_pipeline_4, output, OUT, DDR_CLK_b, 512, PUSH)
MANAGER_NODE_IO(Stream_39_pipeline_4, input, IN, DDR_CLK_c, 512, PUSH)
MANAGER_NODE_IO(Stream_39_pipeline_4, output, OUT, DDR_CLK_c, 512, PUSH)
MANAGER_NODE_IO(Stream_28_pipeline_4, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_28_pipeline_4, output, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_33_pipeline_4, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_33_pipeline_4, output, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_38_pipeline_4, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_38_pipeline_4, output, OUT, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_60, input, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_60, output, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_64, input, IN, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_64, output, OUT, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_1, input, IN, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_1, output, OUT, PCIE, 32, PUSH)
MANAGER_NODE_IO(Stream_4, input, IN, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_4, output, OUT, PCIE, 32, PUSH)
MANAGER_NODE_IO(Stream_8, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_8, output, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_10, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_10, output, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_12, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_12, output, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_14, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_14, output, OUT, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_20, input, IN, PCIE, 32, PULL)
MANAGER_NODE_IO(Stream_20, output, OUT, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_92, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_92, output, OUT, STREAM, 1536, PUSH)
MANAGER_NODE_IO(Stream_96, input, IN, STREAM, 1536, PULL)
MANAGER_NODE_IO(Stream_96, output, OUT, STREAM, 1536, PUSH)
MANAGER_NODE_IO(Stream_124, input, IN, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_124, output, OUT, PCIE, 128, PUSH)
MANAGER_NODE_IO(Stream_98, input, IN, PCIE, 128, PUSH)
MANAGER_NODE_IO(Stream_98, output, OUT, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_102, input, IN, PCIE, 128, PUSH)
MANAGER_NODE_IO(Stream_102, output, OUT, PCIE, 128, PULL)
MANAGER_NODE_IO(Stream_94, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_94, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_80, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_80, output, OUT, DDR_CLK_b, 544, PULL)
MANAGER_NODE_IO(Stream_84, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_84, output, OUT, DDR_CLK_a, 544, PULL)
MANAGER_NODE_IO(Stream_90, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_90, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_68, input, IN, DDR_CLK_a, 512, PUSH)
MANAGER_NODE_IO(Stream_68, output, OUT, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(Stream_72, input, IN, DDR_CLK_b, 512, PUSH)
MANAGER_NODE_IO(Stream_72, output, OUT, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(Stream_76, input, IN, DDR_CLK_c, 512, PUSH)
MANAGER_NODE_IO(Stream_76, output, OUT, MemoryControllerPro0_clk, 512, PULL)
MANAGER_NODE_IO(Stream_42, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_42, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_46, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_46, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_50, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_50, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_54, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_54, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_58, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_58, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_62, input, IN, STREAM, 64, PUSH)
MANAGER_NODE_IO(Stream_62, output, OUT, MemoryControllerPro0_clk, 64, PUSH)
MANAGER_NODE_IO(Stream_100, input, IN, PCIE, 32, PUSH)
MANAGER_NODE_IO(Stream_100, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_104, input, IN, PCIE, 32, PUSH)
MANAGER_NODE_IO(Stream_104, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_108, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_108, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_112, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_112, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_116, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_116, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_120, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_120, output, OUT, STREAM, 32, PULL)
MANAGER_NODE_IO(Stream_88, input, IN, MemoryControllerPro0_clk, 544, PUSH)
MANAGER_NODE_IO(Stream_88, output, OUT, DDR_CLK_c, 544, PULL)
MANAGER_NODE_IO(Stream_122, input, IN, STREAM, 32, PUSH)
MANAGER_NODE_IO(Stream_122, output, OUT, PCIE, 32, PULL)
#endif

#ifdef MANAGER_STREAM
#define MANAGER_STREAM_PRESENT 1
MANAGER_STREAM(inAT1, inAT1, Stream_98, input, 128)
MANAGER_STREAM(inBT1, inBT1, Stream_102, input, 128)
MANAGER_STREAM(StreamFMAKernel, oDataT1, Stream_90, input, 32)
MANAGER_STREAM(StreamFMAKernel, oDataT2, Stream_94, input, 32)
MANAGER_STREAM(StreamFMAKernel, oDataT3, Stream_122, input, 32)
MANAGER_STREAM(MemoryControllerPro0, Tag_Out, MemoryControllerPro0_IntSource, Tag_In, 1)
MANAGER_STREAM(MemoryControllerPro0, cmd_stream_maxj_b, Stream_28_pipeline_4, input, 544)
MANAGER_STREAM(MemoryControllerInterface_b, read_stream_maxj, Stream_29_pipeline_4, input, 512)
MANAGER_STREAM(MemoryControllerPro0, cmd_stream_maxj_a, Stream_33_pipeline_4, input, 544)
MANAGER_STREAM(MemoryControllerInterface_a, read_stream_maxj, Stream_34_pipeline_4, input, 512)
MANAGER_STREAM(MemoryControllerPro0, cmd_stream_maxj_c, Stream_38_pipeline_4, input, 544)
MANAGER_STREAM(MemoryControllerInterface_c, read_stream_maxj, Stream_39_pipeline_4, input, 512)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_inAT2, cgen_out_0, Stream_42, input, 64)
MANAGER_STREAM(MemoryControllerPro0, read_0, Stream_8, input, 1536)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_inBT2, cgen_out_0, Stream_46, input, 64)
MANAGER_STREAM(MemoryControllerPro0, read_1, Stream_10, input, 1536)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_inAT3, cgen_out_0, Stream_50, input, 64)
MANAGER_STREAM(MemoryControllerPro0, read_2, Stream_12, input, 1536)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_inBT3, cgen_out_0, Stream_54, input, 64)
MANAGER_STREAM(MemoryControllerPro0, read_3, Stream_14, input, 1536)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_oDataT1, cgen_out_0, Stream_58, input, 64)
MANAGER_STREAM(addrgen_cmd_MemoryControllerPro0_oDataT2, cgen_out_0, Stream_62, input, 64)
MANAGER_STREAM(Stream_34_pipeline_4, output, Stream_68, input, 512)
MANAGER_STREAM(Stream_29_pipeline_4, output, Stream_72, input, 512)
MANAGER_STREAM(Stream_39_pipeline_4, output, Stream_76, input, 512)
MANAGER_STREAM(Stream_28_pipeline_4, output, Stream_80, input, 544)
MANAGER_STREAM(Stream_33_pipeline_4, output, Stream_84, input, 544)
MANAGER_STREAM(Stream_38_pipeline_4, output, Stream_88, input, 544)
MANAGER_STREAM(Stream_60, output, Stream_92, input, 1536)
MANAGER_STREAM(Stream_64, output, Stream_96, input, 1536)
MANAGER_STREAM(Stream_1, output, Stream_100, input, 32)
MANAGER_STREAM(Stream_4, output, Stream_104, input, 32)
MANAGER_STREAM(Stream_8, output, Stream_108, input, 32)
MANAGER_STREAM(Stream_10, output, Stream_112, input, 32)
MANAGER_STREAM(Stream_12, output, Stream_116, input, 32)
MANAGER_STREAM(Stream_14, output, Stream_120, input, 32)
MANAGER_STREAM(Stream_20, output, Stream_124, input, 128)
MANAGER_STREAM(Stream_92, output, MemoryControllerPro0, write_0, 1536)
MANAGER_STREAM(Stream_96, output, MemoryControllerPro0, write_1, 1536)
MANAGER_STREAM(Stream_124, output, oDataT3, oDataT3, 128)
MANAGER_STREAM(Stream_98, output, Stream_1, input, 128)
MANAGER_STREAM(Stream_102, output, Stream_4, input, 128)
MANAGER_STREAM(Stream_94, output, Stream_64, input, 32)
MANAGER_STREAM(Stream_80, output, MemoryControllerInterface_b, cmd_stream_maxj, 544)
MANAGER_STREAM(Stream_84, output, MemoryControllerInterface_a, cmd_stream_maxj, 544)
MANAGER_STREAM(Stream_90, output, Stream_60, input, 32)
MANAGER_STREAM(Stream_68, output, MemoryControllerPro0, read_stream_maxj_a, 512)
MANAGER_STREAM(Stream_72, output, MemoryControllerPro0, read_stream_maxj_b, 512)
MANAGER_STREAM(Stream_76, output, MemoryControllerPro0, read_stream_maxj_c, 512)
MANAGER_STREAM(Stream_42, output, MemoryControllerPro0, read_command_0, 64)
MANAGER_STREAM(Stream_46, output, MemoryControllerPro0, read_command_1, 64)
MANAGER_STREAM(Stream_50, output, MemoryControllerPro0, read_command_2, 64)
MANAGER_STREAM(Stream_54, output, MemoryControllerPro0, read_command_3, 64)
MANAGER_STREAM(Stream_58, output, MemoryControllerPro0, write_command_0, 64)
MANAGER_STREAM(Stream_62, output, MemoryControllerPro0, write_command_1, 64)
MANAGER_STREAM(Stream_100, output, StreamFMAKernel, inAT1, 32)
MANAGER_STREAM(Stream_104, output, StreamFMAKernel, inBT1, 32)
MANAGER_STREAM(Stream_108, output, StreamFMAKernel, inAT2, 32)
MANAGER_STREAM(Stream_112, output, StreamFMAKernel, inBT2, 32)
MANAGER_STREAM(Stream_116, output, StreamFMAKernel, inAT3, 32)
MANAGER_STREAM(Stream_120, output, StreamFMAKernel, inBT3, 32)
MANAGER_STREAM(Stream_88, output, MemoryControllerInterface_c, cmd_stream_maxj, 544)
MANAGER_STREAM(Stream_122, output, Stream_20, input, 32)
#endif

#ifdef MANAGER_NODE_STACK_TRACE
#define MANAGER_NODE_STACK_TRACE_PRESENT 1
MANAGER_NODE_STACK_TRACE(StreamFMAKernel, "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
MANAGER_NODE_STACK_TRACE(inAT1, "com.maxeler.platform.max5.manager.Max5ManagerBase.addStreamFromCPU(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:26)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
MANAGER_NODE_STACK_TRACE(inBT1, "com.maxeler.platform.max5.manager.Max5ManagerBase.addStreamFromCPU(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:27)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
MANAGER_NODE_STACK_TRACE(oDataT3, "com.maxeler.platform.max5.manager.Max5ManagerBase.addStreamToCPU(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:52)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
MANAGER_NODE_STACK_TRACE(MemoryControllerPro0, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(MemoryControllerPro0_IntSource, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(MemoryControllerInterface_b, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(MemoryControllerInterface_a, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(MemoryControllerInterface_c, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_inAT2, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_inBT2, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_inAT3, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_inBT3, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_oDataT1, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(addrgen_cmd_MemoryControllerPro0_oDataT2, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_34_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_29_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_39_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_28_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_33_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_38_pipeline_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_60, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_64, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_1, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_4, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_8, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_10, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_12, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_14, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_20, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_92, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_96, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_124, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_98, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_102, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_94, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_80, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_84, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_90, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_68, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_72, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_76, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_42, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_46, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_50, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_54, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_58, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_62, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_100, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_104, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_108, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_112, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_116, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_120, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_88, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
MANAGER_NODE_STACK_TRACE(Stream_122, "com.maxeler.platform.max5.manager.Max5ManagerBase.build(Unknown Source)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:61)\n")
#endif


#ifdef MANAGER_NODE_PROPERTY
#define MANAGER_NODE_PROPERTY_PRESENT 1
MANAGER_NODE_PROPERTY(StreamFMAKernel, control_pipelining_depth, 2)
#endif


#ifdef KERNEL_CORE
#define KERNEL_CORE_PRESENT 1
KERNEL_CORE(StreamFMAKernel)
#endif

#ifdef KERNEL_HOST_CONTROLLED
#define KERNEL_HOST_CONTROLLED_PRESENT 1
KERNEL_HOST_CONTROLLED(StreamFMAKernel, StreamFMAKernel)
#endif

#ifdef DEBUG_INPUT_BITS
#define DEBUG_INPUT_BITS_PRESENT 1
DEBUG_INPUT_BITS(StreamFMAKernel, inAT1, 0)
DEBUG_INPUT_BITS(StreamFMAKernel, inBT1, 1)
DEBUG_INPUT_BITS(StreamFMAKernel, inAT2, 2)
DEBUG_INPUT_BITS(StreamFMAKernel, inBT2, 3)
DEBUG_INPUT_BITS(StreamFMAKernel, inAT3, 4)
DEBUG_INPUT_BITS(StreamFMAKernel, inBT3, 5)
#endif

#ifdef DEBUG_OUTPUT_BITS
#define DEBUG_OUTPUT_BITS_PRESENT 1
DEBUG_OUTPUT_BITS(StreamFMAKernel, oDataT1, 0)
DEBUG_OUTPUT_BITS(StreamFMAKernel, oDataT2, 1)
DEBUG_OUTPUT_BITS(StreamFMAKernel, oDataT3, 2)
#endif

#ifdef MANAGER_NODE_CPP_SIM_MODEL_CTOR
#define MANAGER_NODE_CPP_SIM_MODEL_CTOR_PRESENT 1
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_oDataT2, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2, "addrgen_cmd_MemoryControllerPro0_oDataT2")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(inAT1, PCIePushSourceSync16, "inAT1")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_oDataT1, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1, "addrgen_cmd_MemoryControllerPro0_oDataT1")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_inBT2, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2, "addrgen_cmd_MemoryControllerPro0_inBT2")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(inBT1, PCIePushSourceSync16, "inBT1")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_inAT3, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3, "addrgen_cmd_MemoryControllerPro0_inAT3")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_inBT3, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3, "addrgen_cmd_MemoryControllerPro0_inBT3")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(addrgen_cmd_MemoryControllerPro0_inAT2, maxcompilersim::state_machine::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2, "addrgen_cmd_MemoryControllerPro0_inAT2")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_58, FifoPushToPushSync, "Stream_58", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_50, FifoPushToPushSync, "Stream_50", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_42, FifoPushToPushSync, "Stream_42", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_98, FifoPushToPullSync, "Stream_98", false, 512, 128)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_62, FifoPushToPushSync, "Stream_62", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_54, FifoPushToPushSync, "Stream_54", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_46, FifoPushToPushSync, "Stream_46", false, 512, 64)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_102, FifoPushToPullSync, "Stream_102", false, 512, 128)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_4, DualAspectMuxSync, "Stream_4", 32, 4)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_1, DualAspectMuxSync, "Stream_1", 32, 4)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_104, FifoPushToPullSync, "Stream_104", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_100, FifoPushToPullSync, "Stream_100", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_96, PullToPushAdapterSync, "Stream_96")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_28_pipeline_4, PipelineSync, "Stream_28_pipeline_4", 4, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_80, FifoPushToPullSync, "Stream_80", false, 512, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(MemoryControllerInterface_b, LMemSim, "MemoryControllerInterface_b", ConfigFactory<LMemMax5LimaConfig>::getConfig(0, "_b", 3, 0))
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_29_pipeline_4, PipelineSync, "Stream_29_pipeline_4", 4, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_72, FifoPushToPullSync, "Stream_72", false, 512, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_84, FifoPushToPullSync, "Stream_84", false, 512, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(MemoryControllerInterface_a, LMemSim, "MemoryControllerInterface_a", ConfigFactory<LMemMax5LimaConfig>::getConfig(0, "_a", 3, 1))
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_34_pipeline_4, PipelineSync, "Stream_34_pipeline_4", 4, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_68, FifoPushToPullSync, "Stream_68", false, 512, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_90, FifoPushToPullSync, "Stream_90", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_60, DualAspectRegSync, "Stream_60", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_92, PullToPushAdapterSync, "Stream_92")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_8, DualAspectMuxSync, "Stream_8", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_108, FifoPushToPullSync, "Stream_108", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_112, FifoPushToPullSync, "Stream_112", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_124, PullToPushAdapterSync, "Stream_124")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(oDataT3, PCIePushSinkSync16, "oDataT3")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_10, DualAspectMuxSync, "Stream_10", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_39_pipeline_4, PipelineSync, "Stream_39_pipeline_4", 4, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_76, FifoPushToPullSync, "Stream_76", false, 512, 512)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(MemoryControllerPro0, maxcompilersim::state_machine::ManagerBlockSM_MemoryControllerPro0, "MemoryControllerPro0")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(MemoryControllerPro0_IntSource, McpInterruptSource, "MemoryControllerPro0_IntSource")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_12, DualAspectMuxSync, "Stream_12", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_14, DualAspectMuxSync, "Stream_14", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_38_pipeline_4, PipelineSync, "Stream_38_pipeline_4", 4, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_33_pipeline_4, PipelineSync, "Stream_33_pipeline_4", 4, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_116, FifoPushToPullSync, "Stream_116", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_120, FifoPushToPullSync, "Stream_120", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_88, FifoPushToPullSync, "Stream_88", false, 512, 544)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(StreamFMAKernel, StreamFMAKernel, "StreamFMAKernel")
MANAGER_NODE_CPP_SIM_MODEL_CTOR(MemoryControllerInterface_c, LMemSim, "MemoryControllerInterface_c", ConfigFactory<LMemMax5LimaConfig>::getConfig(0, "_c", 3, 2))
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_122, FifoPushToPullSync, "Stream_122", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_94, FifoPushToPullSync, "Stream_94", false, 512, 32)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_20, DualAspectRegSync, "Stream_20", 32, 4)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(Stream_64, DualAspectRegSync, "Stream_64", 32, 48)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(CapabilityReg, CapRegs, "CapabilityReg", 0, 2, 1, 0, 0, 0, 0, 0, 160)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(ifpga, IFPGARegs)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(sfa, SFARegs)
MANAGER_NODE_CPP_SIM_MODEL_CTOR(ChecksumMemory, ChecksumMem, "ChecksumMemory", "5677d622f2daecc91b0561585ae87653a418e3bb53c0a22186ca7832455db10b")
#endif

#ifdef MANAGER_NODE_CPP_SIM_MODEL_SETUP
#define MANAGER_NODE_CPP_SIM_MODEL_SETUP_PRESENT 1
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_almost_empty, 6, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_done, 6, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_empty, 6, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_read, 6, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_read_pipe_dbg, 18, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_ctld_request, 6, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_done_out, 1, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_fill_level, 4, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_flush_level, 4, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_flush_start, 1, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_flush_start_level, 4, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_flushing, 1, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_full_level, 4, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_out_stall, 3, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_out_valid, 3, 0)
MANAGER_NODE_CPP_SIM_MODEL_SETUP(StreamFMAKernel, addDebugRegister, reg_dbg_stall_vector, 3, 0)
#endif

#ifdef PCIE_STREAM
#define PCIE_STREAM_PRESENT 1
PCIE_STREAM(inAT1, STREAM_FROM_HOST, 0)
PCIE_STREAM(inBT1, STREAM_FROM_HOST, 1)
PCIE_STREAM(oDataT3, STREAM_TO_HOST, 0)
#endif








#ifdef REG
#define REG_PRESENT 1
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Addr_En, 0x0, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_BlockSize_X, 0x1, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_CmdSize, 0x6, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Offset_0, 0x7, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Start_X_Addr, 0xb, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Wrap_X, 0xf, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Addr_En, 0x13, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_BlockSize_X, 0x14, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_CmdSize, 0x19, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Offset_0, 0x1a, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Start_X_Addr, 0x1e, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Wrap_X, 0x22, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Addr_En, 0x26, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_BlockSize_X, 0x27, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_CmdSize, 0x2c, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Offset_0, 0x2d, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Start_X_Addr, 0x31, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Wrap_X, 0x35, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Addr_En, 0x39, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_BlockSize_X, 0x3a, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_CmdSize, 0x3f, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Offset_0, 0x40, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Start_X_Addr, 0x44, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Wrap_X, 0x48, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Addr_En, 0x4c, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_BlockSize_X, 0x4d, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_CmdSize, 0x52, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Offset_0, 0x53, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Start_X_Addr, 0x57, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Wrap_X, 0x5b, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Addr_En, 0x5f, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_BlockSize_X, 0x60, 5, hwOffsetFix(33, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_CmdSize, 0x65, 1, hwOffsetFix(8, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Offset_0, 0x66, 4, hwOffsetFix(31, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Start_X_Addr, 0x6a, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Wrap_X, 0x6e, 4, hwOffsetFix(32, 0, UNSIGNED))
REG(MemoryControllerPro0.Mcp_Int_Disable_OR, 0x72, 1, hwOffsetFix(6, 0, UNSIGNED))
REG(MemoryControllerPro0.Mcp_Int_Enable_AND, 0x73, 1, hwOffsetFix(6, 0, UNSIGNED))
REG(StreamFMAKernel.io_inAT1_force_disabled, 0x74, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_inBT1_force_disabled, 0x75, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_inAT2_force_disabled, 0x76, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_inBT2_force_disabled, 0x77, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_inAT3_force_disabled, 0x78, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_inBT3_force_disabled, 0x79, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_oDataT1_force_disabled, 0x7a, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_oDataT2_force_disabled, 0x7b, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.io_oDataT3_force_disabled, 0x7c, 1, hwOffsetFix(1, 0, UNSIGNED))
REG(StreamFMAKernel.run_cycle_count, 0x7d, 6, hwOffsetFix(48, 0, UNSIGNED))
REG(StreamFMAKernel.current_run_cycle_count, 0x83, 6, hwOffsetFix(48, 0, UNSIGNED))
REG(StreamFMAKernel.dbg_ctld_almost_empty, 0x89, 1, hwBits(6))
REG(StreamFMAKernel.dbg_ctld_done, 0x8a, 1, hwBits(6))
REG(StreamFMAKernel.dbg_ctld_empty, 0x8b, 1, hwBits(6))
REG(StreamFMAKernel.dbg_ctld_read, 0x8c, 1, hwBits(6))
REG(StreamFMAKernel.dbg_ctld_read_pipe_dbg, 0x8d, 3, hwBits(18))
REG(StreamFMAKernel.dbg_ctld_request, 0x90, 1, hwBits(6))
REG(StreamFMAKernel.dbg_done_out, 0x91, 1, hwBits(1))
REG(StreamFMAKernel.dbg_fill_level, 0x92, 1, hwBits(4))
REG(StreamFMAKernel.dbg_flush_level, 0x93, 1, hwBits(4))
REG(StreamFMAKernel.dbg_flush_start, 0x94, 1, hwBits(1))
REG(StreamFMAKernel.dbg_flush_start_level, 0x95, 1, hwBits(4))
REG(StreamFMAKernel.dbg_flushing, 0x96, 1, hwBits(1))
REG(StreamFMAKernel.dbg_full_level, 0x97, 1, hwBits(4))
REG(StreamFMAKernel.dbg_out_stall, 0x98, 1, hwBits(3))
REG(StreamFMAKernel.dbg_out_valid, 0x99, 1, hwBits(3))
REG(StreamFMAKernel.dbg_stall_vector, 0x9a, 1, hwBits(3))
REG(ifpga.ifpga_ctrl, 0x9b, 1, hwBits(8))
REG(SignalForwardingAdapter.SFA_FORWARD_EN, 0x9c, 4, hwBits(32))
#endif

#ifdef REG_V2
#define REG_V2_PRESENT 1
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Addr_En, 0x0, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_BlockSize_X, 0x1, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_CmdSize, 0x6, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Offset_0, 0x7, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Start_X_Addr, 0xb, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT2.AGen_Wrap_X, 0xf, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Addr_En, 0x13, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_BlockSize_X, 0x14, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_CmdSize, 0x19, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Offset_0, 0x1a, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Start_X_Addr, 0x1e, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_oDataT1.AGen_Wrap_X, 0x22, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Addr_En, 0x26, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_BlockSize_X, 0x27, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_CmdSize, 0x2c, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Offset_0, 0x2d, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Start_X_Addr, 0x31, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT2.AGen_Wrap_X, 0x35, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Addr_En, 0x39, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_BlockSize_X, 0x3a, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_CmdSize, 0x3f, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Offset_0, 0x40, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Start_X_Addr, 0x44, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT3.AGen_Wrap_X, 0x48, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Addr_En, 0x4c, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_BlockSize_X, 0x4d, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_CmdSize, 0x52, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Offset_0, 0x53, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Start_X_Addr, 0x57, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inBT3.AGen_Wrap_X, 0x5b, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Addr_En, 0x5f, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_BlockSize_X, 0x60, 5, hwOffsetFix(33, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_CmdSize, 0x65, 1, hwOffsetFix(8, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Offset_0, 0x66, 4, hwOffsetFix(31, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Start_X_Addr, 0x6a, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(addrgen_cmd_MemoryControllerPro0_inAT2.AGen_Wrap_X, 0x6e, 4, hwOffsetFix(32, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(MemoryControllerPro0.Mcp_Int_Disable_OR, 0x72, 1, hwOffsetFix(6, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(MemoryControllerPro0.Mcp_Int_Enable_AND, 0x73, 1, hwOffsetFix(6, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(StreamFMAKernel.io_inAT1_force_disabled, 0x74, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_inBT1_force_disabled, 0x75, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_inAT2_force_disabled, 0x76, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_inBT2_force_disabled, 0x77, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_inAT3_force_disabled, 0x78, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_inBT3_force_disabled, 0x79, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_oDataT1_force_disabled, 0x7a, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_oDataT2_force_disabled, 0x7b, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.io_oDataT3_force_disabled, 0x7c, 1, hwOffsetFix(1, 0, UNSIGNED), HOST_WRITE_ONLY, true)
REG_V2(StreamFMAKernel.run_cycle_count, 0x7d, 6, hwOffsetFix(48, 0, UNSIGNED), HOST_WRITE_ONLY, false)
REG_V2(StreamFMAKernel.current_run_cycle_count, 0x83, 6, hwOffsetFix(48, 0, UNSIGNED), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_almost_empty, 0x89, 1, hwBits(6), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_done, 0x8a, 1, hwBits(6), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_empty, 0x8b, 1, hwBits(6), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_read, 0x8c, 1, hwBits(6), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_read_pipe_dbg, 0x8d, 3, hwBits(18), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_ctld_request, 0x90, 1, hwBits(6), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_done_out, 0x91, 1, hwBits(1), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_fill_level, 0x92, 1, hwBits(4), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_flush_level, 0x93, 1, hwBits(4), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_flush_start, 0x94, 1, hwBits(1), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_flush_start_level, 0x95, 1, hwBits(4), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_flushing, 0x96, 1, hwBits(1), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_full_level, 0x97, 1, hwBits(4), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_out_stall, 0x98, 1, hwBits(3), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_out_valid, 0x99, 1, hwBits(3), HOST_READ_ONLY, false)
REG_V2(StreamFMAKernel.dbg_stall_vector, 0x9a, 1, hwBits(3), HOST_READ_ONLY, false)
REG_V2(ifpga.ifpga_ctrl, 0x9b, 1, hwBits(8), HOST_READ_WRITE, false)
REG_V2(SignalForwardingAdapter.SFA_FORWARD_EN, 0x9c, 4, hwBits(32), HOST_READ_WRITE, false)
#endif




#ifdef CHECKSUM
#define CHECKSUM_PRESENT 1
CHECKSUM("5677d622f2daecc91b0561585ae87653a418e3bb53c0a22186ca7832455db10b")
#endif

#ifdef MANAGER_MEMCTL
#define MANAGER_MEMCTL_PRESENT 1
MANAGER_MEMCTL(MemoryControllerPro0, MemoryControllerPro0.Mcp, 192, 0)
#endif

#ifdef MANAGER_MEMCTL_CONTROL_GROUP
#define MANAGER_MEMCTL_CONTROL_GROUP_PRESENT 1
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_inAT2, addrgen_cmd_MemoryControllerPro0_inAT2.AGen, LINEAR_1D)
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_inBT2, addrgen_cmd_MemoryControllerPro0_inBT2.AGen, LINEAR_1D)
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_inAT3, addrgen_cmd_MemoryControllerPro0_inAT3.AGen, LINEAR_1D)
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_inBT3, addrgen_cmd_MemoryControllerPro0_inBT3.AGen, LINEAR_1D)
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_oDataT1, addrgen_cmd_MemoryControllerPro0_oDataT1.AGen, LINEAR_1D)
MANAGER_MEMCTL_CONTROL_GROUP(MemoryControllerPro0, cmd_MemoryControllerPro0_oDataT2, addrgen_cmd_MemoryControllerPro0_oDataT2.AGen, LINEAR_1D)
#endif

#ifdef MANAGER_MEMCTL_DATA_STREAM
#define MANAGER_MEMCTL_DATA_STREAM_PRESENT 1
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_inAT2, inAT2, 0, 0, READ)
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_inBT2, inBT2, 0, 1, READ)
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_inAT3, inAT3, 0, 2, READ)
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_inBT3, inBT3, 0, 3, READ)
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_oDataT1, oDataT1, 0, 4, WRITE)
MANAGER_MEMCTL_DATA_STREAM(MemoryControllerPro0, cmd_MemoryControllerPro0_oDataT2, oDataT2, 0, 5, WRITE)
#endif

#ifdef CAPABILITY
#define CAPABILITY_PRESENT 1
CAPABILITY(LIMAREV, LIMAREVA)
CAPABILITY(LIMARAM, DDR4_48GB)
CAPABILITY(LIMAFPGA, xcVU9P_FLGB2104_2_E)
#endif

#ifdef DEFINE_DESIGN_NAME
#define DESIGN_NAME StreamFMA
#endif /* DEFINE_DESIGN_NAME */

#ifndef SLIC_NO_DECLARATIONS
/**\file */
#ifndef SLIC_DECLARATIONS_StreamFMA_H
#define SLIC_DECLARATIONS_StreamFMA_H
#include "MaxSLiCInterface.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#define StreamFMA_DYNAMIC_CLOCKS_ENABLED (0)
#define StreamFMA_PCIE_ALIGNMENT (16)


/*----------------------------------------------------------------------------*/
/*---------------------------- Interface default -----------------------------*/
/*----------------------------------------------------------------------------*/




/**
 * \brief Basic static function for the interface 'default'.
 * 
 * \param [in] ticks_StreamFMAKernel The number of ticks for which kernel "StreamFMAKernel" will run.
 * \param [in] instream_inAT1 Stream "inAT1".
 * \param [in] instream_size_inAT1 The size of the stream instream_inAT1 in bytes.
 * \param [in] instream_inBT1 Stream "inBT1".
 * \param [in] instream_size_inBT1 The size of the stream instream_inBT1 in bytes.
 * \param [out] outstream_oDataT3 Stream "oDataT3".
 * \param [in] outstream_size_oDataT3 The size of the stream outstream_oDataT3 in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: array size, in bytes.
 */
void StreamFMA(
	uint64_t ticks_StreamFMAKernel,
	const void *instream_inAT1,
	size_t instream_size_inAT1,
	const void *instream_inBT1,
	size_t instream_size_inBT1,
	void *outstream_oDataT3,
	size_t outstream_size_oDataT3,
	size_t lmem_address_MemoryControllerPro0_inAT2,
	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
	size_t lmem_address_MemoryControllerPro0_inAT3,
	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
	size_t lmem_address_MemoryControllerPro0_inBT2,
	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
	size_t lmem_address_MemoryControllerPro0_inBT3,
	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
	size_t lmem_address_MemoryControllerPro0_oDataT1,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
	size_t lmem_address_MemoryControllerPro0_oDataT2,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2);

/**
 * \brief Basic static non-blocking function for the interface 'default'.
 * 
 * Schedule to run on an engine and return immediately.
 * The status of the run can be checked either by ::max_wait or ::max_nowait;
 * note that one of these *must* be called, so that associated memory can be released.
 * 
 * 
 * \param [in] ticks_StreamFMAKernel The number of ticks for which kernel "StreamFMAKernel" will run.
 * \param [in] instream_inAT1 Stream "inAT1".
 * \param [in] instream_size_inAT1 The size of the stream instream_inAT1 in bytes.
 * \param [in] instream_inBT1 Stream "inBT1".
 * \param [in] instream_size_inBT1 The size of the stream instream_inBT1 in bytes.
 * \param [out] outstream_oDataT3 Stream "oDataT3".
 * \param [in] outstream_size_oDataT3 The size of the stream outstream_oDataT3 in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: array size, in bytes.
 * \param [in] lmem_address_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: base address, in bytes.
 * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: array size, in bytes.
 * \return A handle on the execution status, or NULL in case of error.
 */
max_run_t *StreamFMA_nonblock(
	uint64_t ticks_StreamFMAKernel,
	const void *instream_inAT1,
	size_t instream_size_inAT1,
	const void *instream_inBT1,
	size_t instream_size_inBT1,
	void *outstream_oDataT3,
	size_t outstream_size_oDataT3,
	size_t lmem_address_MemoryControllerPro0_inAT2,
	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
	size_t lmem_address_MemoryControllerPro0_inAT3,
	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
	size_t lmem_address_MemoryControllerPro0_inBT2,
	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
	size_t lmem_address_MemoryControllerPro0_inBT3,
	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
	size_t lmem_address_MemoryControllerPro0_oDataT1,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
	size_t lmem_address_MemoryControllerPro0_oDataT2,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2);

/**
 * \brief Advanced static interface, structure for the engine interface 'default'
 * 
 */
typedef struct { 
	uint64_t ticks_StreamFMAKernel; /**<  [in] The number of ticks for which kernel "StreamFMAKernel" will run. */
	const void *instream_inAT1; /**<  [in] Stream "inAT1". */
	size_t instream_size_inAT1; /**<  [in] The size of the stream instream_inAT1 in bytes. */
	const void *instream_inBT1; /**<  [in] Stream "inBT1". */
	size_t instream_size_inBT1; /**<  [in] The size of the stream instream_inBT1 in bytes. */
	void *outstream_oDataT3; /**<  [out] Stream "oDataT3". */
	size_t outstream_size_oDataT3; /**<  [in] The size of the stream outstream_oDataT3 in bytes. */
	size_t lmem_address_MemoryControllerPro0_inAT2; /**<  [in] Linear LMem control for "inAT2" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_inAT2; /**<  [in] Linear LMem control for "inAT2" stream: array size, in bytes. */
	size_t lmem_address_MemoryControllerPro0_inAT3; /**<  [in] Linear LMem control for "inAT3" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_inAT3; /**<  [in] Linear LMem control for "inAT3" stream: array size, in bytes. */
	size_t lmem_address_MemoryControllerPro0_inBT2; /**<  [in] Linear LMem control for "inBT2" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_inBT2; /**<  [in] Linear LMem control for "inBT2" stream: array size, in bytes. */
	size_t lmem_address_MemoryControllerPro0_inBT3; /**<  [in] Linear LMem control for "inBT3" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_inBT3; /**<  [in] Linear LMem control for "inBT3" stream: array size, in bytes. */
	size_t lmem_address_MemoryControllerPro0_oDataT1; /**<  [in] Linear LMem control for "oDataT1" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1; /**<  [in] Linear LMem control for "oDataT1" stream: array size, in bytes. */
	size_t lmem_address_MemoryControllerPro0_oDataT2; /**<  [in] Linear LMem control for "oDataT2" stream: base address, in bytes. */
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2; /**<  [in] Linear LMem control for "oDataT2" stream: array size, in bytes. */
} StreamFMA_actions_t;

/**
 * \brief Advanced static function for the interface 'default'.
 * 
 * \param [in] engine The engine on which the actions will be executed.
 * \param [in,out] interface_actions Actions to be executed.
 */
void StreamFMA_run(
	max_engine_t *engine,
	StreamFMA_actions_t *interface_actions);

/**
 * \brief Advanced static non-blocking function for the interface 'default'.
 *
 * Schedule the actions to run on the engine and return immediately.
 * The status of the run can be checked either by ::max_wait or ::max_nowait;
 * note that one of these *must* be called, so that associated memory can be released.
 *
 * 
 * \param [in] engine The engine on which the actions will be executed.
 * \param [in] interface_actions Actions to be executed.
 * \return A handle on the execution status of the actions, or NULL in case of error.
 */
max_run_t *StreamFMA_run_nonblock(
	max_engine_t *engine,
	StreamFMA_actions_t *interface_actions);

/**
 * \brief Group run advanced static function for the interface 'default'.
 * 
 * \param [in] group Group to use.
 * \param [in,out] interface_actions Actions to run.
 *
 * Run the actions on the first device available in the group.
 */
void StreamFMA_run_group(max_group_t *group, StreamFMA_actions_t *interface_actions);

/**
 * \brief Group run advanced static non-blocking function for the interface 'default'.
 * 
 *
 * Schedule the actions to run on the first device available in the group and return immediately.
 * The status of the run must be checked with ::max_wait. 
 * Note that use of ::max_nowait is prohibited with non-blocking running on groups:
 * see the ::max_run_group_nonblock documentation for more explanation.
 *
 * \param [in] group Group to use.
 * \param [in] interface_actions Actions to run.
 * \return A handle on the execution status of the actions, or NULL in case of error.
 */
max_run_t *StreamFMA_run_group_nonblock(max_group_t *group, StreamFMA_actions_t *interface_actions);

/**
 * \brief Array run advanced static function for the interface 'default'.
 * 
 * \param [in] engarray The array of devices to use.
 * \param [in,out] interface_actions The array of actions to run.
 *
 * Run the array of actions on the array of engines.  The length of interface_actions
 * must match the size of engarray.
 */
void StreamFMA_run_array(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[]);

/**
 * \brief Array run advanced static non-blocking function for the interface 'default'.
 * 
 *
 * Schedule to run the array of actions on the array of engines, and return immediately.
 * The length of interface_actions must match the size of engarray.
 * The status of the run can be checked either by ::max_wait or ::max_nowait;
 * note that one of these *must* be called, so that associated memory can be released.
 *
 * \param [in] engarray The array of devices to use.
 * \param [in] interface_actions The array of actions to run.
 * \return A handle on the execution status of the actions, or NULL in case of error.
 */
max_run_t *StreamFMA_run_array_nonblock(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[]);

/**
 * \brief Converts a static-interface action struct into a dynamic-interface max_actions_t struct.
 *
 * Note that this is an internal utility function used by other functions in the static interface.
 *
 * \param [in] maxfile The maxfile to use.
 * \param [in] interface_actions The interface-specific actions to run.
 * \return The dynamic-interface actions to run, or NULL in case of error.
 */
max_actions_t* StreamFMA_convert(max_file_t *maxfile, StreamFMA_actions_t *interface_actions);

/**
 * \brief Initialise a maxfile.
 */
max_file_t* StreamFMA_init(void);

/* Error handling functions */
int StreamFMA_has_errors(void);
const char* StreamFMA_get_errors(void);
void StreamFMA_clear_errors(void);
/* Free statically allocated maxfile data */
void StreamFMA_free(void);
/* returns: -1 = error running command; 0 = no error reported */
int StreamFMA_simulator_start(void);
/* returns: -1 = error running command; 0 = no error reported */
int StreamFMA_simulator_stop(void);

#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* SLIC_DECLARATIONS_StreamFMA_H */

#endif /* SLIC_NO_DECLARATIONS */

#ifdef PHOTON_NODE_DATA
#define PHOTON_NODE_DATA_PRESENT 1
PHOTON_NODE_DATA(StreamFMAKernel, 22, NodeInputMappedReg, "Scalar input (io_oDataT1_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 23, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 0, NodeInputMappedReg, "Scalar input (io_inAT1_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 1, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 2, NodeInput, "Input(inAT1)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 3, NodeInputMappedReg, "Scalar input (io_inBT1_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 4, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 5, NodeInput, "Input(inBT1)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 18, NodeAdd, "+", "com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:27)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 25, NodeOutput, "Output(oDataT1)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 27, NodeInputMappedReg, "Scalar input (io_oDataT2_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 28, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 6, NodeInputMappedReg, "Scalar input (io_inAT2_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 7, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 8, NodeInput, "Input(inAT2)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 9, NodeInputMappedReg, "Scalar input (io_inBT2_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 10, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 11, NodeInput, "Input(inBT2)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 19, NodeMul, "*", "com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.mul(DFEVar.java:1118)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:28)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 30, NodeOutput, "Output(oDataT2)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 32, NodeInputMappedReg, "Scalar input (io_oDataT3_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 33, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 12, NodeInputMappedReg, "Scalar input (io_inAT3_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 13, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 14, NodeInput, "Input(inAT3)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 15, NodeInputMappedReg, "Scalar input (io_inBT3_force_disabled)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 16, NodeNot, "~", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 17, NodeInput, "Input(inBT3)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 20, NodeAdd, "+", "com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:29)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 35, NodeOutput, "Output(oDataT3)", "com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)\nperfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 40, NodeConstantRawBits, "{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 50, NodeConstantRawBits, "{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 37, NodeConstantRawBits, "{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 38, NodeCounter, "Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 39, NodeStreamOffset, "stream offset: 1", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 41, NodeOutputMappedReg, "Scalar output (current_run_cycle_count)", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 49, NodeConstantRawBits, "{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 43, NodeConstantRawBits, "{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 44, NodeCounter, "Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 46, NodeInputMappedReg, "Scalar input (run_cycle_count)", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 48, NodeEqInlined, "==", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
PHOTON_NODE_DATA(StreamFMAKernel, 45, NodeFlush, "flush on trigger", "com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)\nperfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)\nperfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)\n")
#endif

#ifdef SLIC_USE_DEFINITIONS
#include <stdio.h>
#include <math.h>
#include <pthread.h>
#include <string.h>
#include <unistd.h>
#include <stdlib.h>
static max_file_t *stored_maxfile = NULL;
static max_engine_t *stored_engine = NULL;
static char *stored_error = NULL;
static int stored_has_error = 0;
static pthread_once_t slic_bs_is_initialised = PTHREAD_ONCE_INIT;

static void set_error(const char *error_str)
{
	stored_has_error = 1; 
	if(stored_error == NULL) {
		stored_error = strdup(error_str);
	} else {
		char *nerr = malloc(strlen(stored_error) + strlen(error_str) + 2);
		sprintf(nerr, "%s\n%s", stored_error, error_str);
		free(stored_error);
		stored_error = nerr;
	}
}
static void set_error_and_free(char *error_str){
	set_error(error_str);
	free(error_str);
}
int StreamFMA_has_errors(void)
{	return stored_has_error; }
const char* StreamFMA_get_errors(void)
{	return stored_error; }
void StreamFMA_clear_errors(void)
{
	free(stored_error);
	stored_error = NULL;
	stored_has_error = 0;
}

static char StreamFMA_use_simulation[16];
static void StreamFMA_def_use_simulation(void)
{
	long pid = ((long) getpid()) % 100000;
	snprintf(StreamFMA_use_simulation, 16, "StreamFM_%05ld_", pid);
}
static const char *StreamFMA_check_use_simulation(void)
{
	StreamFMA_def_use_simulation();
	const char *use_sim = max_config_get_string(MAX_CONFIG_USE_SIMULATION);
	if (use_sim == NULL) {
		use_sim = StreamFMA_use_simulation;
		max_config_set_string(MAX_CONFIG_USE_SIMULATION, use_sim);
	}
	return use_sim;
}

static int StreamFMA_simulation_launch = 0;
int StreamFMA_simulator_start(void)
{
	int retval = 0;
	const char *use_sim = StreamFMA_check_use_simulation();
	char buff[1024];
	snprintf(buff, 1024, "PATH=simutils:$PATH maxcompilersim -d 1 -n %s -c MAX5C -S simutils restart", use_sim);
	FILE *pipe_fp = popen(buff, "r");
	if (pipe_fp == NULL) {
		strncat(buff, " : failed to execute.", (1024 - strlen(buff)));
		set_error(buff);
		return -1;
	}
	while (fgets(buff, 1024, pipe_fp) != NULL) {
		/* Uncomment this to get simulator command output */
		/* fprintf(stderr, buff); */
		if (strstr(buff, "Error")) {
			set_error(buff);
			retval = -1;
		}
	}
	pclose(pipe_fp);
	return retval;
}

int StreamFMA_simulator_stop(void)
{
	const char *use_sim = StreamFMA_check_use_simulation();
	char buff[1024];
	snprintf(buff, 1024, "PATH=simutils:$PATH maxcompilersim -d 1 -n %s -c MAX5C -S simutils stop", use_sim);
	FILE *pipe_fp = popen(buff, "r");
	if (pipe_fp == NULL) {
		strncat(buff, " : failed to execute.", (1024 - strlen(buff)));
		set_error(buff);
		return -1;
	}
	while (fgets(buff, 1024, pipe_fp) != NULL) {
		/* Uncomment this to get simulator command output */
		/* fprintf(stderr, buff); */
		;
	}
	pclose(pipe_fp);
	return 0;
}

static void StreamFMA_static_init(void) 
{
	stored_maxfile = StreamFMA_init();
	if (stored_maxfile == NULL || !max_ok(stored_maxfile->errors)) {
		stored_maxfile = NULL;
		if(max_config_get_bool(MAX_CONFIG_STATIC_INTERFACE_ABORT_ON_ERROR)) abort();
		else { set_error("Unable to load maxfile"); return; }
	}
	if(!max_ok(max_global_errors())) {
		set_error_and_free(max_errors_trace(max_global_errors()));
		return;
	}
	if(!max_config_get_bool(MAX_CONFIG_STATIC_INTERFACE_ABORT_ON_ERROR))
		max_errors_mode(stored_maxfile->errors, 0);
	time_t timeout_previous = max_load_timeout(stored_maxfile, 30);
	const char *use_sim = StreamFMA_check_use_simulation();
	if (max_ping_daemon(stored_maxfile, use_sim) == 0) {
		int sim_stat = StreamFMA_simulator_start();
		if ((sim_stat == 0) && (max_ping_daemon(stored_maxfile, use_sim) == 1)) {
			StreamFMA_simulation_launch = 1;
		} else {
			set_error("Error: An error occurred while trying to start the simulation infrastructure automatically.");
			set_error("Error: Check that 'use_simulation=<simulator_name>' is set correctly in your SLiC configuration");
			set_error("Error: and that the associated simulated system daemon is running.");
			max_file_free(stored_maxfile);
			stored_maxfile = NULL;
			return;
		}
	}
	stored_engine = max_load(stored_maxfile, "*");
	if (!max_ok(stored_maxfile->errors)) {
		if(max_config_get_bool(MAX_CONFIG_STATIC_INTERFACE_ABORT_ON_ERROR)) {
			fprintf(stderr, "\nUnable to load engine: aborting now.\n\n");
			fflush(stderr);
			abort();
		} else {
			set_error_and_free(max_errors_trace(stored_maxfile->errors));
			max_file_free(stored_maxfile);
			stored_maxfile = NULL;
			return;
		} 
	} 
	max_load_timeout(stored_maxfile, timeout_previous);
}
void StreamFMA_free(void)
{
	if (stored_engine != NULL) {
		max_unload(stored_engine);
		stored_engine = NULL;
	}
	if (stored_maxfile != NULL) {
		max_file_free(stored_maxfile);
		stored_maxfile = NULL;
	}
	if (stored_error != NULL) {
		free(stored_error);
		stored_error = NULL;
	}
	if (StreamFMA_simulation_launch == 1) {
		int sim_stat = StreamFMA_simulator_stop();
		if (sim_stat != 0 ) {
			fprintf(stderr, "Error stopping simulator.");
		}
		StreamFMA_simulation_launch = 0;
	}
}

static int StreamFMA_get_pcie_alignment(void)
{
#ifdef StreamFMA_PCIE_ALIGNMENT
	return ((StreamFMA_PCIE_ALIGNMENT < 1) ? 16 : StreamFMA_PCIE_ALIGNMENT);
#else
	return 16;
#endif
}

static int StreamFMA_check_aligned(const void *data)
{
	uintptr_t pointer = (uintptr_t) data;
	int alignment = StreamFMA_get_pcie_alignment();
	return (pointer % alignment) ? 1 : 0;
}

static void *StreamFMA_malloc_aligned(const size_t size)
{
	void *ptr;
	int alignment = StreamFMA_get_pcie_alignment();
	posix_memalign(&ptr, alignment, size);
	return ptr;
}



/*----------------------------------------------------------------------------*/
/*---------------------------- Interface default -----------------------------*/
/*----------------------------------------------------------------------------*/



#define CHECK_ERRORS_ST(ST, RET) if(!max_ok(ST->errors)) { if(max_config_get_bool(MAX_CONFIG_STATIC_INTERFACE_ABORT_ON_ERROR)) { fprintf(stderr, "%s\n", max_errors_trace(ST->errors)); abort(); } set_error_and_free(max_errors_trace(ST->errors)); return RET; } 
#define CHECK_NULL(VALUE, MESSAGE, RET) if(VALUE == NULL) { if (max_config_get_bool(MAX_CONFIG_STATIC_INTERFACE_ABORT_ON_ERROR)) { fprintf(stderr, "%s\n%s\n", (stored_error == NULL) ? "" : stored_error, MESSAGE); abort(); } set_error(MESSAGE); return RET; }

 
typedef struct StreamFMA_callback_stream {
	uint8_t *user_ptr;
	uint8_t *aligned_ptr;
	size_t   size;
	int      is_output;
} StreamFMA_callback_stream_t;

typedef struct StreamFMA_callback_data {
	StreamFMA_callback_stream_t stream[3]; 
	int count;
	int max_count;
} StreamFMA_callback_data_t;

static void StreamFMA_callback_internal(void *cb_data)
{
	StreamFMA_callback_data_t *data = (StreamFMA_callback_data_t*) cb_data;
	for (int i = 0 ; i < data->count ; i++ ) {
		StreamFMA_callback_stream_t *s = &data->stream[i];
		if (s->is_output && (s->size > 0)) {
			memcpy(s->user_ptr, s->aligned_ptr, s->size);
		}
		free(s->aligned_ptr);
	}
	free(data);
}

static max_actions_t* StreamFMA_convert_internal(
	max_file_t *maxfile,
	StreamFMA_actions_t *interface_actions,
	int  is_internal_call,
	void (**callback_func)(void*),
	void **callback_data)
{
	max_actions_t *actions = max_actions_init(maxfile, NULL);
	if(actions == NULL) return NULL;

#define CHECK_ERRORS if(!max_ok(actions->errors)) { set_error_and_free(max_errors_trace(actions->errors)); return NULL; } 

	StreamFMA_callback_data_t *cb_data = NULL;
	int use_callback = (callback_func != NULL) && (callback_data != NULL);
	if (use_callback) {
		cb_data = malloc(sizeof(StreamFMA_callback_data_t));
		if (cb_data == NULL) {
			fprintf(stderr, "Unable to allocate memory for stream callback data in function StreamFMA_convert_internal\n");
			return NULL;
		}
		cb_data->max_count = 3;
		cb_data->count     = 0;
		*callback_data     = cb_data;
		*callback_func     = &StreamFMA_callback_internal;
	}

	/* code for scalar StreamFMAKernel.run_cycle_count */
	uint64_t ticks_StreamFMAKernel = interface_actions->ticks_StreamFMAKernel;
	max_set_ticks(actions, "StreamFMAKernel", ticks_StreamFMAKernel);
	CHECK_ERRORS;
	/* end of code for scalar StreamFMAKernel.run_cycle_count*/
	
	/* code for stream inAT1 */
	size_t instream_size_inAT1 = interface_actions->instream_size_inAT1;
	if (instream_size_inAT1 > 0) {
		const void *stream_ptr = interface_actions->instream_inAT1;
		if (use_callback && (1 == StreamFMA_check_aligned(interface_actions->instream_inAT1))) {
			void *aligned_instream_inAT1 = malloc(instream_size_inAT1);
			if (aligned_instream_inAT1 == NULL) {
				max_report_error_slic(actions->errors, __FILE__, __LINE__, 526, "Failed to allocate aligned memory for stream 'inAT1'");
				CHECK_ERRORS;
			}
			(&cb_data->stream[cb_data->count])->user_ptr    = (uint8_t*) interface_actions->instream_inAT1;
			(&cb_data->stream[cb_data->count])->aligned_ptr = (uint8_t*) aligned_instream_inAT1;
			(&cb_data->stream[cb_data->count])->size        = instream_size_inAT1;
			(&cb_data->stream[cb_data->count])->is_output   = 0;
			cb_data->count += 1;
			memcpy(aligned_instream_inAT1, interface_actions->instream_inAT1, instream_size_inAT1);
			stream_ptr = aligned_instream_inAT1;
		}
		max_queue_input(actions, "inAT1", stream_ptr, instream_size_inAT1);
		CHECK_ERRORS;
	}
	/* end of code for stream inAT1 */
	
	/* code for stream inBT1 */
	size_t instream_size_inBT1 = interface_actions->instream_size_inBT1;
	if (instream_size_inBT1 > 0) {
		const void *stream_ptr = interface_actions->instream_inBT1;
		if (use_callback && (1 == StreamFMA_check_aligned(interface_actions->instream_inBT1))) {
			void *aligned_instream_inBT1 = malloc(instream_size_inBT1);
			if (aligned_instream_inBT1 == NULL) {
				max_report_error_slic(actions->errors, __FILE__, __LINE__, 526, "Failed to allocate aligned memory for stream 'inBT1'");
				CHECK_ERRORS;
			}
			(&cb_data->stream[cb_data->count])->user_ptr    = (uint8_t*) interface_actions->instream_inBT1;
			(&cb_data->stream[cb_data->count])->aligned_ptr = (uint8_t*) aligned_instream_inBT1;
			(&cb_data->stream[cb_data->count])->size        = instream_size_inBT1;
			(&cb_data->stream[cb_data->count])->is_output   = 0;
			cb_data->count += 1;
			memcpy(aligned_instream_inBT1, interface_actions->instream_inBT1, instream_size_inBT1);
			stream_ptr = aligned_instream_inBT1;
		}
		max_queue_input(actions, "inBT1", stream_ptr, instream_size_inBT1);
		CHECK_ERRORS;
	}
	/* end of code for stream inBT1 */
	
	/* code for stream oDataT3 */
	size_t outstream_size_oDataT3 = interface_actions->outstream_size_oDataT3;
	if (outstream_size_oDataT3 > 0) {
		void *stream_ptr = interface_actions->outstream_oDataT3;
		if (use_callback && (1 == StreamFMA_check_aligned(interface_actions->outstream_oDataT3))) {
			void *aligned_outstream_oDataT3 = malloc(outstream_size_oDataT3);
			if (aligned_outstream_oDataT3 == NULL) {
				max_report_error_slic(actions->errors, __FILE__, __LINE__, 526, "Failed to allocate aligned memory for stream 'oDataT3'");
				CHECK_ERRORS;
			}
			(&cb_data->stream[cb_data->count])->user_ptr    = (uint8_t*) interface_actions->outstream_oDataT3;
			(&cb_data->stream[cb_data->count])->aligned_ptr = (uint8_t*) aligned_outstream_oDataT3;
			(&cb_data->stream[cb_data->count])->size        = outstream_size_oDataT3;
			(&cb_data->stream[cb_data->count])->is_output   = 1;
			cb_data->count += 1;
			stream_ptr = aligned_outstream_oDataT3;
		}
		max_queue_output(actions, "oDataT3", stream_ptr, outstream_size_oDataT3);
		CHECK_ERRORS;
	}
	/* end of code for stream oDataT3 */
	
	/* code for linear memory-stream "inAT2" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_inAT2 = interface_actions->lmem_address_MemoryControllerPro0_inAT2;
	size_t lmem_arr_size_MemoryControllerPro0_inAT2 = interface_actions->lmem_arr_size_MemoryControllerPro0_inAT2;
	int lmem_burst_size_MemoryControllerPro0_inAT2 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_inAT2 % lmem_burst_size_MemoryControllerPro0_inAT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inAT2 parameter 'lmem_address_MemoryControllerPro0_inAT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_inAT2, lmem_burst_size_MemoryControllerPro0_inAT2 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_inAT2 % lmem_burst_size_MemoryControllerPro0_inAT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inAT2 parameter 'lmem_arr_size_MemoryControllerPro0_inAT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_inAT2, lmem_burst_size_MemoryControllerPro0_inAT2 );
	}
	if (lmem_arr_size_MemoryControllerPro0_inAT2 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "inAT2", lmem_address_MemoryControllerPro0_inAT2, lmem_arr_size_MemoryControllerPro0_inAT2);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "inAT2");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "inAT2" in memory-controller "MemoryControllerPro0" */
	
	/* code for linear memory-stream "inAT3" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_inAT3 = interface_actions->lmem_address_MemoryControllerPro0_inAT3;
	size_t lmem_arr_size_MemoryControllerPro0_inAT3 = interface_actions->lmem_arr_size_MemoryControllerPro0_inAT3;
	int lmem_burst_size_MemoryControllerPro0_inAT3 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_inAT3 % lmem_burst_size_MemoryControllerPro0_inAT3) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inAT3 parameter 'lmem_address_MemoryControllerPro0_inAT3' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_inAT3, lmem_burst_size_MemoryControllerPro0_inAT3 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_inAT3 % lmem_burst_size_MemoryControllerPro0_inAT3) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inAT3 parameter 'lmem_arr_size_MemoryControllerPro0_inAT3' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_inAT3, lmem_burst_size_MemoryControllerPro0_inAT3 );
	}
	if (lmem_arr_size_MemoryControllerPro0_inAT3 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "inAT3", lmem_address_MemoryControllerPro0_inAT3, lmem_arr_size_MemoryControllerPro0_inAT3);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "inAT3");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "inAT3" in memory-controller "MemoryControllerPro0" */
	
	/* code for linear memory-stream "inBT2" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_inBT2 = interface_actions->lmem_address_MemoryControllerPro0_inBT2;
	size_t lmem_arr_size_MemoryControllerPro0_inBT2 = interface_actions->lmem_arr_size_MemoryControllerPro0_inBT2;
	int lmem_burst_size_MemoryControllerPro0_inBT2 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_inBT2 % lmem_burst_size_MemoryControllerPro0_inBT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inBT2 parameter 'lmem_address_MemoryControllerPro0_inBT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_inBT2, lmem_burst_size_MemoryControllerPro0_inBT2 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_inBT2 % lmem_burst_size_MemoryControllerPro0_inBT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inBT2 parameter 'lmem_arr_size_MemoryControllerPro0_inBT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_inBT2, lmem_burst_size_MemoryControllerPro0_inBT2 );
	}
	if (lmem_arr_size_MemoryControllerPro0_inBT2 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "inBT2", lmem_address_MemoryControllerPro0_inBT2, lmem_arr_size_MemoryControllerPro0_inBT2);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "inBT2");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "inBT2" in memory-controller "MemoryControllerPro0" */
	
	/* code for linear memory-stream "inBT3" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_inBT3 = interface_actions->lmem_address_MemoryControllerPro0_inBT3;
	size_t lmem_arr_size_MemoryControllerPro0_inBT3 = interface_actions->lmem_arr_size_MemoryControllerPro0_inBT3;
	int lmem_burst_size_MemoryControllerPro0_inBT3 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_inBT3 % lmem_burst_size_MemoryControllerPro0_inBT3) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inBT3 parameter 'lmem_address_MemoryControllerPro0_inBT3' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_inBT3, lmem_burst_size_MemoryControllerPro0_inBT3 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_inBT3 % lmem_burst_size_MemoryControllerPro0_inBT3) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem inBT3 parameter 'lmem_arr_size_MemoryControllerPro0_inBT3' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_inBT3, lmem_burst_size_MemoryControllerPro0_inBT3 );
	}
	if (lmem_arr_size_MemoryControllerPro0_inBT3 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "inBT3", lmem_address_MemoryControllerPro0_inBT3, lmem_arr_size_MemoryControllerPro0_inBT3);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "inBT3");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "inBT3" in memory-controller "MemoryControllerPro0" */
	
	/* code for linear memory-stream "oDataT1" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_oDataT1 = interface_actions->lmem_address_MemoryControllerPro0_oDataT1;
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1 = interface_actions->lmem_arr_size_MemoryControllerPro0_oDataT1;
	int lmem_burst_size_MemoryControllerPro0_oDataT1 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_oDataT1 % lmem_burst_size_MemoryControllerPro0_oDataT1) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem oDataT1 parameter 'lmem_address_MemoryControllerPro0_oDataT1' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_oDataT1, lmem_burst_size_MemoryControllerPro0_oDataT1 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_oDataT1 % lmem_burst_size_MemoryControllerPro0_oDataT1) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem oDataT1 parameter 'lmem_arr_size_MemoryControllerPro0_oDataT1' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_oDataT1, lmem_burst_size_MemoryControllerPro0_oDataT1 );
	}
	if (lmem_arr_size_MemoryControllerPro0_oDataT1 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "oDataT1", lmem_address_MemoryControllerPro0_oDataT1, lmem_arr_size_MemoryControllerPro0_oDataT1);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "oDataT1");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "oDataT1" in memory-controller "MemoryControllerPro0" */
	
	/* code for linear memory-stream "oDataT2" in memory-controller "MemoryControllerPro0" */
	size_t lmem_address_MemoryControllerPro0_oDataT2 = interface_actions->lmem_address_MemoryControllerPro0_oDataT2;
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2 = interface_actions->lmem_arr_size_MemoryControllerPro0_oDataT2;
	int lmem_burst_size_MemoryControllerPro0_oDataT2 = max_get_burst_size(maxfile, "MemoryControllerPro0");
	if ( (lmem_address_MemoryControllerPro0_oDataT2 % lmem_burst_size_MemoryControllerPro0_oDataT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem oDataT2 parameter 'lmem_address_MemoryControllerPro0_oDataT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_address_MemoryControllerPro0_oDataT2, lmem_burst_size_MemoryControllerPro0_oDataT2 );
	}
	if ( (lmem_arr_size_MemoryControllerPro0_oDataT2 % lmem_burst_size_MemoryControllerPro0_oDataT2) != 0 ) {
		fprintf(stdout, "\nSLiC Error: %s:%d : LMem oDataT2 parameter 'lmem_arr_size_MemoryControllerPro0_oDataT2' is set to %zd bytes; it must be a multiple of %d bytes\n", __FILE__, __LINE__, lmem_arr_size_MemoryControllerPro0_oDataT2, lmem_burst_size_MemoryControllerPro0_oDataT2 );
	}
	if (lmem_arr_size_MemoryControllerPro0_oDataT2 > 0) {
		max_memctl_linear(actions, "MemoryControllerPro0", "oDataT2", lmem_address_MemoryControllerPro0_oDataT2, lmem_arr_size_MemoryControllerPro0_oDataT2);
	} else {
		max_ignore_memctl(actions, "MemoryControllerPro0", "oDataT2");
	}
	CHECK_ERRORS;
	/* end of code for linear memory-stream "oDataT2" in memory-controller "MemoryControllerPro0" */
	
	if (use_callback && cb_data->count == 0) {
		*callback_data = NULL;
		*callback_func = NULL;
		free(cb_data);
	}
	return actions;
#undef CHECK_ERRORS
}

void StreamFMA(
	uint64_t ticks_StreamFMAKernel,
	const void *instream_inAT1,
	size_t instream_size_inAT1,
	const void *instream_inBT1,
	size_t instream_size_inBT1,
	void *outstream_oDataT3,
	size_t outstream_size_oDataT3,
	size_t lmem_address_MemoryControllerPro0_inAT2,
	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
	size_t lmem_address_MemoryControllerPro0_inAT3,
	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
	size_t lmem_address_MemoryControllerPro0_inBT2,
	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
	size_t lmem_address_MemoryControllerPro0_inBT3,
	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
	size_t lmem_address_MemoryControllerPro0_oDataT1,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
	size_t lmem_address_MemoryControllerPro0_oDataT2,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2)
{
	(void) pthread_once(&slic_bs_is_initialised, StreamFMA_static_init);
	CHECK_NULL(stored_maxfile, "Maxfile was not loaded", );
	max_run_t *run = StreamFMA_nonblock(ticks_StreamFMAKernel, instream_inAT1, instream_size_inAT1, instream_inBT1, instream_size_inBT1, outstream_oDataT3, outstream_size_oDataT3, lmem_address_MemoryControllerPro0_inAT2, lmem_arr_size_MemoryControllerPro0_inAT2, lmem_address_MemoryControllerPro0_inAT3, lmem_arr_size_MemoryControllerPro0_inAT3, lmem_address_MemoryControllerPro0_inBT2, lmem_arr_size_MemoryControllerPro0_inBT2, lmem_address_MemoryControllerPro0_inBT3, lmem_arr_size_MemoryControllerPro0_inBT3, lmem_address_MemoryControllerPro0_oDataT1, lmem_arr_size_MemoryControllerPro0_oDataT1, lmem_address_MemoryControllerPro0_oDataT2, lmem_arr_size_MemoryControllerPro0_oDataT2);
	CHECK_NULL(run, "Unable to run actions", );
	max_wait(run);
}

max_run_t *StreamFMA_nonblock(
	uint64_t ticks_StreamFMAKernel,
	const void *instream_inAT1,
	size_t instream_size_inAT1,
	const void *instream_inBT1,
	size_t instream_size_inBT1,
	void *outstream_oDataT3,
	size_t outstream_size_oDataT3,
	size_t lmem_address_MemoryControllerPro0_inAT2,
	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
	size_t lmem_address_MemoryControllerPro0_inAT3,
	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
	size_t lmem_address_MemoryControllerPro0_inBT2,
	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
	size_t lmem_address_MemoryControllerPro0_inBT3,
	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
	size_t lmem_address_MemoryControllerPro0_oDataT1,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
	size_t lmem_address_MemoryControllerPro0_oDataT2,
	size_t lmem_arr_size_MemoryControllerPro0_oDataT2)
{
	StreamFMA_actions_t interface_actions;
	interface_actions.ticks_StreamFMAKernel = ticks_StreamFMAKernel;
	interface_actions.instream_inAT1 = instream_inAT1;
	interface_actions.instream_size_inAT1 = instream_size_inAT1;
	interface_actions.instream_inBT1 = instream_inBT1;
	interface_actions.instream_size_inBT1 = instream_size_inBT1;
	interface_actions.outstream_oDataT3 = outstream_oDataT3;
	interface_actions.outstream_size_oDataT3 = outstream_size_oDataT3;
	interface_actions.lmem_address_MemoryControllerPro0_inAT2 = lmem_address_MemoryControllerPro0_inAT2;
	interface_actions.lmem_arr_size_MemoryControllerPro0_inAT2 = lmem_arr_size_MemoryControllerPro0_inAT2;
	interface_actions.lmem_address_MemoryControllerPro0_inAT3 = lmem_address_MemoryControllerPro0_inAT3;
	interface_actions.lmem_arr_size_MemoryControllerPro0_inAT3 = lmem_arr_size_MemoryControllerPro0_inAT3;
	interface_actions.lmem_address_MemoryControllerPro0_inBT2 = lmem_address_MemoryControllerPro0_inBT2;
	interface_actions.lmem_arr_size_MemoryControllerPro0_inBT2 = lmem_arr_size_MemoryControllerPro0_inBT2;
	interface_actions.lmem_address_MemoryControllerPro0_inBT3 = lmem_address_MemoryControllerPro0_inBT3;
	interface_actions.lmem_arr_size_MemoryControllerPro0_inBT3 = lmem_arr_size_MemoryControllerPro0_inBT3;
	interface_actions.lmem_address_MemoryControllerPro0_oDataT1 = lmem_address_MemoryControllerPro0_oDataT1;
	interface_actions.lmem_arr_size_MemoryControllerPro0_oDataT1 = lmem_arr_size_MemoryControllerPro0_oDataT1;
	interface_actions.lmem_address_MemoryControllerPro0_oDataT2 = lmem_address_MemoryControllerPro0_oDataT2;
	interface_actions.lmem_arr_size_MemoryControllerPro0_oDataT2 = lmem_arr_size_MemoryControllerPro0_oDataT2;
	(void) pthread_once(&slic_bs_is_initialised, StreamFMA_static_init);
	CHECK_NULL(stored_maxfile, "Maxfile was not loaded", NULL);
	void (*cb_func)(void*) = NULL;
	void  *cb_data         = NULL;
	max_actions_t *actions = StreamFMA_convert_internal(stored_maxfile, &interface_actions, 1, &cb_func, &cb_data);
	CHECK_NULL(actions, "Unable to build actions", NULL);
	max_validate(actions);
	CHECK_ERRORS_ST(actions, NULL);
	CHECK_ERRORS_ST(stored_engine, NULL);
	max_run_t *run;
	if (cb_func == NULL) {
		run = max_run_nonblock(stored_engine, actions);
	} else {
		run = max_run_nonblock_with_cb(stored_engine, actions, cb_func, cb_data);
	}
	CHECK_NULL(run, "Unable to run actions", NULL);
	CHECK_ERRORS_ST(actions, NULL);
	max_actions_free(actions);
	return run;
}

void StreamFMA_run(
	max_engine_t *engine,
	StreamFMA_actions_t *interface_actions)
{
	max_run_t *run = StreamFMA_run_nonblock(engine, interface_actions);
	CHECK_NULL(run, "Unable to run actions", );
	max_wait(run);
}

max_run_t *StreamFMA_run_nonblock(
	max_engine_t *engine,
	StreamFMA_actions_t *interface_actions)
{
	max_file_t *maxfile = max_engine_get_max_file(engine); 
	void (*cb_func)(void*) = NULL;
	void  *cb_data         = NULL;
	max_actions_t *actions = StreamFMA_convert_internal(maxfile, interface_actions, 1, &cb_func, &cb_data);
	CHECK_NULL(actions, "Unable to build actions", NULL);
	max_validate(actions);
	CHECK_ERRORS_ST(actions, NULL);
	max_run_t *run;
	if (cb_func == NULL) {
		run = max_run_nonblock(engine, actions);
	} else {
		run = max_run_nonblock_with_cb(engine, actions, cb_func, cb_data);
	}
	CHECK_NULL(run, "Unable to run actions", NULL);
	max_actions_free(actions);
	return run;
}


/**
 * \brief Group run advanced static function for the interface 'default'.
 * 
 * \param [in] group Group to use.
 * \param [in,out] interface_actions Actions to run.
 *
 * Run the actions on the first device available in the group.
 */
void StreamFMA_run_group(max_group_t *group, StreamFMA_actions_t *interface_actions)
{
	max_run_t *run = StreamFMA_run_group_nonblock(group, interface_actions);
	CHECK_NULL(run, "Unable to run actions", );
	max_wait(run);
}


/**
 * \brief Group run advanced static non-blocking function for the interface 'default'.
 * 
 *
 * Schedule the actions to run on the first device available in the group and return immediately.
 * The status of the run must be checked with ::max_wait. 
 * Note that use of ::max_nowait is prohibited with non-blocking running on groups:
 * see the ::max_run_group_nonblock documentation for more explanation.
 *
 * \param [in] group Group to use.
 * \param [in] interface_actions Actions to run.
 * \return A handle on the execution status of the actions, or NULL in case of error.
 */
max_run_t *StreamFMA_run_group_nonblock(max_group_t *group, StreamFMA_actions_t *interface_actions)
{
	max_file_t *maxfile = max_group_get_max_file(group);
	max_actions_t *actions = StreamFMA_convert_internal(maxfile, interface_actions, 1, NULL, NULL);
	if(actions == NULL) return NULL;
	if(!max_ok(actions->errors)) return NULL;
	max_validate(actions);
	max_run_t *run = max_run_group_nonblock(group, actions);
	max_actions_free(actions);
	return run;
}


/**
 * \brief Array run advanced static function for the interface 'default'.
 * 
 * \param [in] engarray The array of devices to use.
 * \param [in,out] interface_actions The array of actions to run.
 *
 * Run the array of actions on the array of engines.  The length of interface_actions
 * must match the size of engarray.
 */
void StreamFMA_run_array(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[])
{
	max_run_t *run = StreamFMA_run_array_nonblock(engarray, interface_actions);
	CHECK_NULL(run, "Unable to run actions", );
	max_wait(run);
}


/**
 * \brief Array run advanced static non-blocking function for the interface 'default'.
 * 
 *
 * Schedule to run the array of actions on the array of engines, and return immediately.
 * The length of interface_actions must match the size of engarray.
 * The status of the run can be checked either by ::max_wait or ::max_nowait;
 * note that one of these *must* be called, so that associated memory can be released.
 *
 * \param [in] engarray The array of devices to use.
 * \param [in] interface_actions The array of actions to run.
 * \return A handle on the execution status of the actions, or NULL in case of error.
 */
max_run_t *StreamFMA_run_array_nonblock(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[])
{
	max_file_t *maxfile = max_engarray_get_max_file(engarray, 0);
	int i;
	max_actarray_t *actarray = max_actarray_init(maxfile, engarray->size);
	if (actarray == NULL) return NULL;
	max_actions_t **arr_actions = malloc(engarray->size * sizeof(max_actions_t*));
	for ( i = 0 ; i < actarray->size; i++ ) {
		max_actions_t *actions = StreamFMA_convert_internal(maxfile, interface_actions[i], 1, NULL, NULL);
		if (actions == NULL) return NULL;
		arr_actions[i] = actions;
		max_set_action(actarray, i, actions);
	}
	max_run_t *run = max_run_array_nonblock(engarray, actarray);
	for ( i = 0 ; i < actarray->size ; i++ ) { max_actions_free(arr_actions[i]); }
	max_actarray_free(actarray);
	free(arr_actions);
	return run;
}


/**
 * \brief Converts a static-interface action struct into a dynamic-interface max_actions_t struct.
 *
 * Note that this is an internal utility function used by other functions in the static interface.
 *
 * \param [in] maxfile The maxfile to use.
 * \param [in] interface_actions The interface-specific actions to run.
 * \return The dynamic-interface actions to run, or NULL in case of error.
 */
max_actions_t* StreamFMA_convert(max_file_t *maxfile, StreamFMA_actions_t *interface_actions)
{
	return StreamFMA_convert_internal(maxfile, interface_actions, 0, NULL, NULL);
}

#undef CHECK_ERRORS_ST
#undef CHECK_NULL



#endif /* SLIC_USE_DEFINITIONS */

#ifdef SLIC_DYNAMIC_CODE
SLIC_MODE_START(default)	
SLIC_MODE_END(default)

#endif /* SLIC_DYNAMIC_CODE */

#ifdef SKIN_META_DATA
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#endif /* SKIN_META_DATA */

#ifdef SLIC_B64_DEFINITIONS
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#endif /* SLIC_B64_DEFINITIONS */

#ifdef SLIC_EXTRA_FILES
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#endif /* SLIC_EXTRA_FILES */

#ifdef PHOTON_NODE_ADD_DATA
#define PHOTON_NODE_ADD_DATA_PRESENT 1
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 22, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 23, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 0, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 1, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 2, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 3, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 4, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 5, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 18, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 25, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 27, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 28, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 6, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 7, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 8, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 9, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 10, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 11, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 19, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 30, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 32, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 33, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 12, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 13, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 14, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 15, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 16, "SquashFactor", 1.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 17, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 20, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 35, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 40, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 50, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 37, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 38, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 39, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 41, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 49, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 43, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 44, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 46, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 48, "SquashFactor", 0.0)
PHOTON_NODE_ADD_DATA(StreamFMAKernel, 45, "SquashFactor", 0.0)
#endif

#ifdef MAXFILE_SIGNATURE
#define MAXFILE_SIGNATURE_PRESENT 1
MAXFILE_SIGNATURE("302d02150088772342d2d888822b583166fd04736983822f1b02143417323058ae7f98fb7b34570f80ed9ff6bfc31e")
#endif

#ifdef PARAM
#define PARAM_PRESENT 1
PARAM(TIMING_SCORE, 0)
#endif

#ifdef BITSTREAM
#error You are using too old sliccompile to compile this maxfile.
#endif
#ifdef BITSTREAM_NEW
#define BITSTREAM_COMPRESSED 1
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#endif

#ifdef PARAM
PARAM(BITSTREAM_SIZE, 638528)
#endif