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Manager_StreamFMA_pullpush.dot

Manager_StreamFMA_pullpush.dot 31 KB
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  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT2" ROWSPAN="1" COLSPAN="1">inAT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT2" ROWSPAN="1" COLSPAN="1">inBT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT3" ROWSPAN="1" COLSPAN="1">inAT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT3" ROWSPAN="1" COLSPAN="1">inBT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT1" ROWSPAN="1" COLSPAN="1">oDataT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT2" ROWSPAN="1" COLSPAN="1">oDataT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. inAT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inAT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    4. 

  4. inBT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inBT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    5. 

  5. oDataT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : oDataT3</TD></TR></TABLE>>];
    6. 

  6. MemoryControllerPro0[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_a" ROWSPAN="1" COLSPAN="1">read_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_b" ROWSPAN="1" COLSPAN="1">read_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_c" ROWSPAN="1" COLSPAN="1">read_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_0" ROWSPAN="1" COLSPAN="1">read_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_1" ROWSPAN="1" COLSPAN="1">read_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_2" ROWSPAN="1" COLSPAN="1">read_command_2<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_3" ROWSPAN="1" COLSPAN="1">read_command_3<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_0" ROWSPAN="1" COLSPAN="1">write_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_1" ROWSPAN="1" COLSPAN="1">write_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_0" ROWSPAN="1" COLSPAN="1">write_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_1" ROWSPAN="1" COLSPAN="1">write_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_MemoryControllerPro0 : MemoryControllerPro0</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_0" ROWSPAN="1" COLSPAN="1">read_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_1" ROWSPAN="1" COLSPAN="1">read_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_2" ROWSPAN="1" COLSPAN="1">read_2<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_3" ROWSPAN="1" COLSPAN="1">read_3<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="Tag_Out" ROWSPAN="1" COLSPAN="1">Tag_Out<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_a" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_b" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_c" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR></TABLE>>];
    7. 

  7. MemoryControllerPro0_IntSource[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="Tag_In" ROWSPAN="1" COLSPAN="1">Tag_In<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryInterruptSource : MemoryControllerPro0_IntSource</TD></TR></TABLE>>];
    8. 

  8. MemoryControllerInterface_b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_b : MemoryControllerInterface_b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    9. 

  9. MemoryControllerInterface_a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_a : MemoryControllerInterface_a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    10. 

  10. MemoryControllerInterface_c[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_c : MemoryControllerInterface_c</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    11. 

  11. addrgen_cmd_MemoryControllerPro0_inAT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2 : addrgen_cmd_MemoryControllerPro0_inAT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    12. 

  12. addrgen_cmd_MemoryControllerPro0_inBT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2 : addrgen_cmd_MemoryControllerPro0_inBT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    13. 

  13. addrgen_cmd_MemoryControllerPro0_inAT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3 : addrgen_cmd_MemoryControllerPro0_inAT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    14. 

  14. addrgen_cmd_MemoryControllerPro0_inBT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3 : addrgen_cmd_MemoryControllerPro0_inBT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    15. 

  15. addrgen_cmd_MemoryControllerPro0_oDataT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1 : addrgen_cmd_MemoryControllerPro0_oDataT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    16. 

  16. addrgen_cmd_MemoryControllerPro0_oDataT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2 : addrgen_cmd_MemoryControllerPro0_oDataT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    17. 

  17. Stream_34_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_34_pipeline : Stream_34_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    18. 

  18. Stream_29_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_29_pipeline : Stream_29_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    19. 

  19. Stream_39_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_39_pipeline : Stream_39_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    20. 

  20. Stream_28_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_28_pipeline : Stream_28_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    21. 

  21. Stream_33_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_33_pipeline : Stream_33_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    22. 

  22. Stream_38_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_38_pipeline : Stream_38_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    23. 

  23. Stream_60[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_60</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    24. 

  24. Stream_64[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_64</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    25. 

  25. Stream_1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    26. 

  26. Stream_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    27. 

  27. Stream_8[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_8</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    28. 

  28. Stream_10[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_10</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    29. 

  29. Stream_12[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_12</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    30. 

  30. Stream_14[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_14</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    31. 

  31. Stream_20[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_20</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    32. 

  32. Stream_92[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_92</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    33. 

  33. Stream_96[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_96</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    34. 

  34. Stream_124[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_124</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    35. 

  35. inAT1 -> Stream_1 [headport="input" tailport="inAT1" label="{D{data:1}}"]
    36. 

  36. inBT1 -> Stream_4 [headport="input" tailport="inBT1" label="{D{data:1}}"]
    37. 

  37. StreamFMAKernel -> Stream_60 [headport="input" tailport="oDataT1" label="{D{data:1}}"]
    38. 

  38. StreamFMAKernel -> Stream_64 [headport="input" tailport="oDataT2" label="{D{data:1}}"]
    39. 

  39. StreamFMAKernel -> Stream_20 [headport="input" tailport="oDataT3" label="{D{data:1}}"]
    40. 

  40. MemoryControllerPro0 -> MemoryControllerPro0_IntSource [headport="Tag_In" tailport="Tag_Out" label="{D{data:1}}"]
    41. 

  41. MemoryControllerPro0 -> Stream_28_pipeline_4 [headport="input" tailport="cmd_stream_maxj_b" label="{D{data:1}}"]
    42. 

  42. MemoryControllerInterface_b -> Stream_29_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    43. 

  43. MemoryControllerPro0 -> Stream_33_pipeline_4 [headport="input" tailport="cmd_stream_maxj_a" label="{D{data:1}}"]
    44. 

  44. MemoryControllerInterface_a -> Stream_34_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    45. 

  45. MemoryControllerPro0 -> Stream_38_pipeline_4 [headport="input" tailport="cmd_stream_maxj_c" label="{D{data:1}}"]
    46. 

  46. MemoryControllerInterface_c -> Stream_39_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    47. 

  47. addrgen_cmd_MemoryControllerPro0_inAT2 -> MemoryControllerPro0 [headport="read_command_0" tailport="cgen_out_0" label="{D{data:1}}"]
    48. 

  48. MemoryControllerPro0 -> Stream_8 [headport="input" tailport="read_0" label="{D{data:1}}"]
    49. 

  49. addrgen_cmd_MemoryControllerPro0_inBT2 -> MemoryControllerPro0 [headport="read_command_1" tailport="cgen_out_0" label="{D{data:1}}"]
    50. 

  50. MemoryControllerPro0 -> Stream_10 [headport="input" tailport="read_1" label="{D{data:1}}"]
    51. 

  51. addrgen_cmd_MemoryControllerPro0_inAT3 -> MemoryControllerPro0 [headport="read_command_2" tailport="cgen_out_0" label="{D{data:1}}"]
    52. 

  52. MemoryControllerPro0 -> Stream_12 [headport="input" tailport="read_2" label="{D{data:1}}"]
    53. 

  53. addrgen_cmd_MemoryControllerPro0_inBT3 -> MemoryControllerPro0 [headport="read_command_3" tailport="cgen_out_0" label="{D{data:1}}"]
    54. 

  54. MemoryControllerPro0 -> Stream_14 [headport="input" tailport="read_3" label="{D{data:1}}"]
    55. 

  55. addrgen_cmd_MemoryControllerPro0_oDataT1 -> MemoryControllerPro0 [headport="write_command_0" tailport="cgen_out_0" label="{D{data:1}}"]
    56. 

  56. addrgen_cmd_MemoryControllerPro0_oDataT2 -> MemoryControllerPro0 [headport="write_command_1" tailport="cgen_out_0" label="{D{data:1}}"]
    57. 

  57. Stream_34_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_a" tailport="output" label="{D{data:1}}"]
    58. 

  58. Stream_29_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_b" tailport="output" label="{D{data:1}}"]
    59. 

  59. Stream_39_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_c" tailport="output" label="{D{data:1}}"]
    60. 

  60. Stream_28_pipeline_4 -> MemoryControllerInterface_b [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    61. 

  61. Stream_33_pipeline_4 -> MemoryControllerInterface_a [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    62. 

  62. Stream_38_pipeline_4 -> MemoryControllerInterface_c [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    63. 

  63. Stream_60 -> Stream_92 [headport="input" tailport="output" label="{D{data:1}}"]
    64. 

  64. Stream_64 -> Stream_96 [headport="input" tailport="output" label="{D{data:1}}"]
    65. 

  65. Stream_1 -> StreamFMAKernel [headport="inAT1" tailport="output" label="{D{data:1}}"]
    66. 

  66. Stream_4 -> StreamFMAKernel [headport="inBT1" tailport="output" label="{D{data:1}}"]
    67. 

  67. Stream_8 -> StreamFMAKernel [headport="inAT2" tailport="output" label="{D{data:1}}"]
    68. 

  68. Stream_10 -> StreamFMAKernel [headport="inBT2" tailport="output" label="{D{data:1}}"]
    69. 

  69. Stream_12 -> StreamFMAKernel [headport="inAT3" tailport="output" label="{D{data:1}}"]
    70. 

  70. Stream_14 -> StreamFMAKernel [headport="inBT3" tailport="output" label="{D{data:1}}"]
    71. 

  71. Stream_20 -> Stream_124 [headport="input" tailport="output" label="{D{data:1}}"]
    72. 

  72. Stream_92 -> MemoryControllerPro0 [headport="write_0" tailport="output" label="{D{data:1}}"]
    73. 

  73. Stream_96 -> MemoryControllerPro0 [headport="write_1" tailport="output" label="{D{data:1}}"]
    74. 

  74. Stream_124 -> oDataT3 [headport="oDataT3" tailport="output" label="{D{data:1}}"]
    75. 

  75. }
    76. 

  76.