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Manager_StreamFMA_final.dot

Manager_StreamFMA_final.dot 41 KB
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  1. digraph manager_compiler_graph {
    2. 

  2. StreamFMAKernel[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT2" ROWSPAN="1" COLSPAN="1">inAT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT2" ROWSPAN="1" COLSPAN="1">inBT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inAT3" ROWSPAN="1" COLSPAN="1">inAT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD><TD BGCOLOR="white" BORDER="1" PORT="inBT3" ROWSPAN="1" COLSPAN="1">inBT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1 ael=2</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Kernel : StreamFMAKernel</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT1" ROWSPAN="1" COLSPAN="1">oDataT1<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT2" ROWSPAN="1" COLSPAN="1">oDataT2<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 5</TD></TR></TABLE></TD></TR></TABLE>>];
    3. 

  3. inAT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inAT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inAT1" ROWSPAN="1" COLSPAN="1">inAT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    4. 

  4. inBT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_From_Host : inBT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="inBT1" ROWSPAN="1" COLSPAN="1">inBT1<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    5. 

  5. oDataT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="oDataT3" ROWSPAN="1" COLSPAN="1">oDataT3<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">PCIe_To_Host : oDataT3</TD></TR></TABLE>>];
    6. 

  6. MemoryControllerPro0[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_a" ROWSPAN="1" COLSPAN="1">read_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_b" ROWSPAN="1" COLSPAN="1">read_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj_c" ROWSPAN="1" COLSPAN="1">read_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=512<BR/>PULL el=1 ael=3</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_0" ROWSPAN="1" COLSPAN="1">read_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_1" ROWSPAN="1" COLSPAN="1">read_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_2" ROWSPAN="1" COLSPAN="1">read_command_2<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_command_3" ROWSPAN="1" COLSPAN="1">read_command_3<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_0" ROWSPAN="1" COLSPAN="1">write_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_1" ROWSPAN="1" COLSPAN="1">write_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_0" ROWSPAN="1" COLSPAN="1">write_command_0<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD><TD BGCOLOR="white" BORDER="1" PORT="write_command_1" ROWSPAN="1" COLSPAN="1">write_command_1<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=64<BR/>PUSH 8</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_MemoryControllerPro0 : MemoryControllerPro0</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_0" ROWSPAN="1" COLSPAN="1">read_0<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_1" ROWSPAN="1" COLSPAN="1">read_1<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_2" ROWSPAN="1" COLSPAN="1">read_2<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="read_3" ROWSPAN="1" COLSPAN="1">read_3<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1 ael=8</TD><TD BGCOLOR="white" BORDER="1" PORT="Tag_Out" ROWSPAN="1" COLSPAN="1">Tag_Out<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_a" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_a<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_b" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_b<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj_c" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj_c<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR></TABLE>>];
    7. 

  7. MemoryControllerPro0_IntSource[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="Tag_In" ROWSPAN="1" COLSPAN="1">Tag_In<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=1<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryInterruptSource : MemoryControllerPro0_IntSource</TD></TR></TABLE>>];
    8. 

  8. MemoryControllerInterface_b[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_b : MemoryControllerInterface_b</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    9. 

  9. MemoryControllerInterface_a[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_a : MemoryControllerInterface_a</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    10. 

  10. MemoryControllerInterface_c[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cmd_stream_maxj" ROWSPAN="1" COLSPAN="1">cmd_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=544<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">MemoryControllerInterface_c : MemoryControllerInterface_c</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="read_stream_maxj" ROWSPAN="1" COLSPAN="1">read_stream_maxj<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    11. 

  11. addrgen_cmd_MemoryControllerPro0_inAT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2 : addrgen_cmd_MemoryControllerPro0_inAT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    12. 

  12. addrgen_cmd_MemoryControllerPro0_inBT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2 : addrgen_cmd_MemoryControllerPro0_inBT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    13. 

  13. addrgen_cmd_MemoryControllerPro0_inAT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3 : addrgen_cmd_MemoryControllerPro0_inAT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    14. 

  14. addrgen_cmd_MemoryControllerPro0_inBT3[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3 : addrgen_cmd_MemoryControllerPro0_inBT3</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    15. 

  15. addrgen_cmd_MemoryControllerPro0_oDataT1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1 : addrgen_cmd_MemoryControllerPro0_oDataT1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    16. 

  16. addrgen_cmd_MemoryControllerPro0_oDataT2[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2 : addrgen_cmd_MemoryControllerPro0_oDataT2</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="cgen_out_0" ROWSPAN="1" COLSPAN="1">cgen_out_0<BR/>clk=STREAM (100.0MHz)<BR/>width=64<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    17. 

  17. Stream_34_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_34_pipeline : Stream_34_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_a (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    18. 

  18. Stream_29_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_29_pipeline : Stream_29_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_b (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    19. 

  19. Stream_39_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_39_pipeline : Stream_39_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=DDR_CLK_c (266.6MHz)<BR/>width=512<BR/>PUSH 9</TD></TR></TABLE></TD></TR></TABLE>>];
    20. 

  20. Stream_28_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_28_pipeline : Stream_28_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    21. 

  21. Stream_33_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_33_pipeline : Stream_33_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    22. 

  22. Stream_38_pipeline_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 3</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">Stream_38_pipeline : Stream_38_pipeline_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=MemoryControllerPro0_clk (272.5MHz)<BR/>width=544<BR/>PUSH 11</TD></TR></TABLE></TD></TR></TABLE>>];
    23. 

  23. Stream_60[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_60</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    24. 

  24. Stream_64[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_64</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    25. 

  25. Stream_1[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_1</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    26. 

  26. Stream_4[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_4</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    27. 

  27. Stream_8[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_8</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    28. 

  28. Stream_10[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_10</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    29. 

  29. Stream_12[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_12</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    30. 

  30. Stream_14[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectMux : Stream_14</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=32<BR/>PUSH 2</TD></TR></TABLE></TD></TR></TABLE>>];
    31. 

  31. Stream_20[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=32<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">DualAspectReg : Stream_20</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR></TABLE>>];
    32. 

  32. Stream_92[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_92</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    33. 

  33. Stream_96[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_96</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=STREAM (100.0MHz)<BR/>width=1536<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    34. 

  34. Stream_124[shape=plaintext, label=<<TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="1"><TR><TD BGCOLOR="white" BORDER="0" PORT="inputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="input" ROWSPAN="1" COLSPAN="1">input<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PULL el=1</TD></TR></TABLE></TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="node_info" ROWSPAN="1" COLSPAN="1">StreamPullPushAdapter : Stream_124</TD></TR><TR><TD BGCOLOR="white" BORDER="0" PORT="outputs" ROWSPAN="1" COLSPAN="1"><TABLE  BORDER="1" CELLPADDING="1" CELLSPACING="4"><TR><TD BGCOLOR="white" BORDER="1" PORT="output" ROWSPAN="1" COLSPAN="1">output<BR/>clk=PCIE (125.0MHz)<BR/>width=128<BR/>PUSH 1</TD></TR></TABLE></TD></TR></TABLE>>];
    35. 

  35. Stream_98[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_98<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    36. 

  36. Stream_102[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_102<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    37. 

  37. Stream_94[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_94<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    38. 

  38. Stream_80[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_80<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    39. 

  39. Stream_84[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_84<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    40. 

  40. Stream_90[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_90<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    41. 

  41. Stream_68[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_68<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    42. 

  42. Stream_72[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_72<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    43. 

  43. Stream_76[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_76<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    44. 

  44. Stream_42[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_42<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    45. 

  45. Stream_46[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_46<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    46. 

  46. Stream_50[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_50<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    47. 

  47. Stream_54[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_54<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    48. 

  48. Stream_58[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_58<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    49. 

  49. Stream_62[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_62<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    50. 

  50. Stream_100[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_100<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    51. 

  51. Stream_104[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_104<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    52. 

  52. Stream_108[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_108<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    53. 

  53. Stream_112[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_112<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    54. 

  54. Stream_116[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_116<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    55. 

  55. Stream_120[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_120<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    56. 

  56. Stream_88[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_88<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    57. 

  57. Stream_122[shape=plaintext, label=<<TABLE BORDER="0" CELLSPACING="0" CELLBORDER="1"><TR><TD PORT="input"></TD><TD BORDER="0" ROWSPAN="6" WIDTH="1"></TD></TR><TR><TD></TD></TR><TR><TD>Stream_122<br />(512)</TD></TR><TR><TD></TD></TR><TR><TD></TD></TR><TR HEIGHT="0" CELLPADDING="0" BORDER="0" ><TD CELLPADDING="0" BORDER="0" PORT="output"></TD></TR> </TABLE>>];
    58. 

  58. inAT1 -> Stream_98 [headport="input" tailport="inAT1" label="{D{data:1}}"]
    59. 

  59. inBT1 -> Stream_102 [headport="input" tailport="inBT1" label="{D{data:1}}"]
    60. 

  60. StreamFMAKernel -> Stream_90 [headport="input" tailport="oDataT1" label="{D{data:1}}"]
    61. 

  61. StreamFMAKernel -> Stream_94 [headport="input" tailport="oDataT2" label="{D{data:1}}"]
    62. 

  62. StreamFMAKernel -> Stream_122 [headport="input" tailport="oDataT3" label="{D{data:1}}"]
    63. 

  63. MemoryControllerPro0 -> MemoryControllerPro0_IntSource [headport="Tag_In" tailport="Tag_Out" label="{D{data:1}}"]
    64. 

  64. MemoryControllerPro0 -> Stream_28_pipeline_4 [headport="input" tailport="cmd_stream_maxj_b" label="{D{data:1}}"]
    65. 

  65. MemoryControllerInterface_b -> Stream_29_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    66. 

  66. MemoryControllerPro0 -> Stream_33_pipeline_4 [headport="input" tailport="cmd_stream_maxj_a" label="{D{data:1}}"]
    67. 

  67. MemoryControllerInterface_a -> Stream_34_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    68. 

  68. MemoryControllerPro0 -> Stream_38_pipeline_4 [headport="input" tailport="cmd_stream_maxj_c" label="{D{data:1}}"]
    69. 

  69. MemoryControllerInterface_c -> Stream_39_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"]
    70. 

  70. addrgen_cmd_MemoryControllerPro0_inAT2 -> Stream_42 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    71. 

  71. MemoryControllerPro0 -> Stream_8 [headport="input" tailport="read_0" label="{D{data:1}}"]
    72. 

  72. addrgen_cmd_MemoryControllerPro0_inBT2 -> Stream_46 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    73. 

  73. MemoryControllerPro0 -> Stream_10 [headport="input" tailport="read_1" label="{D{data:1}}"]
    74. 

  74. addrgen_cmd_MemoryControllerPro0_inAT3 -> Stream_50 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    75. 

  75. MemoryControllerPro0 -> Stream_12 [headport="input" tailport="read_2" label="{D{data:1}}"]
    76. 

  76. addrgen_cmd_MemoryControllerPro0_inBT3 -> Stream_54 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    77. 

  77. MemoryControllerPro0 -> Stream_14 [headport="input" tailport="read_3" label="{D{data:1}}"]
    78. 

  78. addrgen_cmd_MemoryControllerPro0_oDataT1 -> Stream_58 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    79. 

  79. addrgen_cmd_MemoryControllerPro0_oDataT2 -> Stream_62 [headport="input" tailport="cgen_out_0" label="{D{data:1}}"]
    80. 

  80. Stream_34_pipeline_4 -> Stream_68 [headport="input" tailport="output" label="{D{data:1}}"]
    81. 

  81. Stream_29_pipeline_4 -> Stream_72 [headport="input" tailport="output" label="{D{data:1}}"]
    82. 

  82. Stream_39_pipeline_4 -> Stream_76 [headport="input" tailport="output" label="{D{data:1}}"]
    83. 

  83. Stream_28_pipeline_4 -> Stream_80 [headport="input" tailport="output" label="{D{data:1}}"]
    84. 

  84. Stream_33_pipeline_4 -> Stream_84 [headport="input" tailport="output" label="{D{data:1}}"]
    85. 

  85. Stream_38_pipeline_4 -> Stream_88 [headport="input" tailport="output" label="{D{data:1}}"]
    86. 

  86. Stream_60 -> Stream_92 [headport="input" tailport="output" label="{D{data:1}}"]
    87. 

  87. Stream_64 -> Stream_96 [headport="input" tailport="output" label="{D{data:1}}"]
    88. 

  88. Stream_1 -> Stream_100 [headport="input" tailport="output" label="{D{data:1}}"]
    89. 

  89. Stream_4 -> Stream_104 [headport="input" tailport="output" label="{D{data:1}}"]
    90. 

  90. Stream_8 -> Stream_108 [headport="input" tailport="output" label="{D{data:1}}"]
    91. 

  91. Stream_10 -> Stream_112 [headport="input" tailport="output" label="{D{data:1}}"]
    92. 

  92. Stream_12 -> Stream_116 [headport="input" tailport="output" label="{D{data:1}}"]
    93. 

  93. Stream_14 -> Stream_120 [headport="input" tailport="output" label="{D{data:1}}"]
    94. 

  94. Stream_20 -> Stream_124 [headport="input" tailport="output" label="{D{data:1}}"]
    95. 

  95. Stream_92 -> MemoryControllerPro0 [headport="write_0" tailport="output" label="{D{data:1}}"]
    96. 

  96. Stream_96 -> MemoryControllerPro0 [headport="write_1" tailport="output" label="{D{data:1}}"]
    97. 

  97. Stream_124 -> oDataT3 [headport="oDataT3" tailport="output" label="{D{data:1}}"]
    98. 

  98. Stream_98 -> Stream_1 [headport="input" tailport="output" label="{D{data:1}}"]
    99. 

  99. Stream_102 -> Stream_4 [headport="input" tailport="output" label="{D{data:1}}"]
    100. 

  100. Stream_94 -> Stream_64 [headport="input" tailport="output" label="{D{data:1}}"]
    101. 

  101. Stream_80 -> MemoryControllerInterface_b [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    102. 

  102. Stream_84 -> MemoryControllerInterface_a [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    103. 

  103. Stream_90 -> Stream_60 [headport="input" tailport="output" label="{D{data:1}}"]
    104. 

  104. Stream_68 -> MemoryControllerPro0 [headport="read_stream_maxj_a" tailport="output" label="{D{data:1}}"]
    105. 

  105. Stream_72 -> MemoryControllerPro0 [headport="read_stream_maxj_b" tailport="output" label="{D{data:1}}"]
    106. 

  106. Stream_76 -> MemoryControllerPro0 [headport="read_stream_maxj_c" tailport="output" label="{D{data:1}}"]
    107. 

  107. Stream_42 -> MemoryControllerPro0 [headport="read_command_0" tailport="output" label="{D{data:1}}"]
    108. 

  108. Stream_46 -> MemoryControllerPro0 [headport="read_command_1" tailport="output" label="{D{data:1}}"]
    109. 

  109. Stream_50 -> MemoryControllerPro0 [headport="read_command_2" tailport="output" label="{D{data:1}}"]
    110. 

  110. Stream_54 -> MemoryControllerPro0 [headport="read_command_3" tailport="output" label="{D{data:1}}"]
    111. 

  111. Stream_58 -> MemoryControllerPro0 [headport="write_command_0" tailport="output" label="{D{data:1}}"]
    112. 

  112. Stream_62 -> MemoryControllerPro0 [headport="write_command_1" tailport="output" label="{D{data:1}}"]
    113. 

  113. Stream_100 -> StreamFMAKernel [headport="inAT1" tailport="output" label="{D{data:1}}"]
    114. 

  114. Stream_104 -> StreamFMAKernel [headport="inBT1" tailport="output" label="{D{data:1}}"]
    115. 

  115. Stream_108 -> StreamFMAKernel [headport="inAT2" tailport="output" label="{D{data:1}}"]
    116. 

  116. Stream_112 -> StreamFMAKernel [headport="inBT2" tailport="output" label="{D{data:1}}"]
    117. 

  117. Stream_116 -> StreamFMAKernel [headport="inAT3" tailport="output" label="{D{data:1}}"]
    118. 

  118. Stream_120 -> StreamFMAKernel [headport="inBT3" tailport="output" label="{D{data:1}}"]
    119. 

  119. Stream_88 -> MemoryControllerInterface_c [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"]
    120. 

  120. Stream_122 -> Stream_20 [headport="input" tailport="output" label="{D{data:1}}"]
    121. 

  121. }
    122. 

  122.