starpu_sgemm_gemm.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 492beed5 33177600 7.077888e+09 2.745578e+03 3.064191e+02 6.616844e+05 1.839335e+09 241
  37. 0b0b0ce8 3686400 2.621440e+08 1.582927e+02 3.333442e+01 3.434951e+04 5.678402e+06 217
  38. 4220e23d 14745600 2.097152e+09 8.206871e+02 1.017181e+02 1.148962e+05 9.574235e+07 140
  39. ####################
  40. # COMB_2
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb2)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 492beed5 33177600 7.077888e+09 2.686428e+03 2.002215e+02 6.716071e+05 1.814247e+09 250
  68. 0b0b0ce8 3686400 2.621440e+08 1.630480e+02 3.438768e+01 3.097912e+04 5.275762e+06 190
  69. 4220e23d 14745600 2.097152e+09 8.448030e+02 7.773742e+01 2.433033e+05 2.072837e+08 288
  70. ####################
  71. # COMB_3
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 1
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda1_impl0 (Comb3)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 492beed5 33177600 7.077888e+09 2.791098e+03 3.147711e+02 6.503258e+05 1.838209e+09 233
  99. 0b0b0ce8 3686400 2.621440e+08 1.624855e+02 3.298013e+01 2.940987e+04 4.975550e+06 181
  100. 4220e23d 14745600 2.097152e+09 8.152506e+02 1.017614e+02 1.173961e+05 9.719839e+07 144
  101. ####################
  102. # COMB_1
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb1)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 492beed5 33177600 7.077888e+09 2.754203e+03 2.682327e+02 6.830422e+05 1.899080e+09 248
  130. 0b0b0ce8 3686400 2.621440e+08 1.622246e+02 3.553894e+01 3.714942e+04 6.315779e+06 229
  131. 4220e23d 14745600 2.097152e+09 8.611626e+02 9.290485e+01 2.411255e+05 2.100651e+08 280
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 0
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cpu0_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 492beed5 33177600 7.077888e+09 1.712078e+05 4.163047e+04 2.773567e+07 5.029326e+12 162
  161. 0b0b0ce8 3686400 2.621440e+08 6.441655e+03 1.152866e+03 3.220827e+05 2.141201e+09 50
  162. 4220e23d 14745600 2.097152e+09 4.927734e+04 1.166029e+04 5.913281e+06 3.077063e+11 120