starpu_dlu_lu_model_12.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. ff82dda0 14745600 0.000000e+00 3.402547e+04 6.005726e+03 7.111323e+06 2.495045e+11 209
  37. 2c1922b7 1638400 0.000000e+00 6.443940e+03 1.476966e+03 1.610985e+05 1.092645e+09 25
  38. d39bff17 6553600 0.000000e+00 1.041247e+04 1.992240e+03 3.092503e+06 3.337940e+10 297
  39. ####################
  40. # COMB_2
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb2)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. ff82dda0 14745600 0.000000e+00 3.238292e+03 4.902889e+02 6.768030e+05 2.241926e+09 209
  68. 2c1922b7 1638400 0.000000e+00 5.889641e+02 1.063542e+02 1.272162e+05 7.736903e+07 216
  69. d39bff17 6553600 0.000000e+00 1.349909e+03 1.936514e+02 2.942801e+05 4.054266e+08 218
  70. ####################
  71. # COMB_1
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 0
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda0_impl0 (Comb1)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. ff82dda0 14745600 0.000000e+00 3.179744e+03 4.016259e+02 6.804652e+05 2.198224e+09 214
  99. 2c1922b7 1638400 0.000000e+00 5.796961e+02 1.048897e+02 1.199971e+05 7.183924e+07 207
  100. d39bff17 6553600 0.000000e+00 1.343917e+03 2.039127e+02 2.244341e+05 3.085646e+08 167
  101. ####################
  102. # COMB_0
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 3
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda3_impl0 (Comb0)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. ff82dda0 14745600 0.000000e+00 3.362936e+03 5.457359e+02 6.524096e+05 2.251791e+09 194
  130. 2c1922b7 1638400 0.000000e+00 5.405600e+02 9.344101e+01 1.513568e+05 8.426217e+07 280
  131. d39bff17 6553600 0.000000e+00 1.275634e+03 1.830051e+02 2.270629e+05 2.956105e+08 178
  132. ####################
  133. # COMB_3
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 2
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda2_impl0 (Comb3)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. ff82dda0 14745600 0.000000e+00 3.306190e+03 4.921154e+02 7.009122e+05 2.368690e+09 212
  161. 2c1922b7 1638400 0.000000e+00 5.641572e+02 1.012475e+02 1.376544e+05 8.015997e+07 244
  162. d39bff17 6553600 0.000000e+00 1.355727e+03 1.656730e+02 2.331851e+05 3.208564e+08 172