starpu_dlu_lu_model_11.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_4
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb4)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 617e5fe6 7372800 0.000000e+00 1.778570e+05 1.735127e+04 1.778570e+06 3.193419e+11 10
  37. cea37d6d 819200 0.000000e+00 5.904224e+03 6.575598e+02 5.668055e+05 3.388055e+09 96
  38. afdd228b 3276800 0.000000e+00 4.953149e+04 6.709149e+03 6.439093e+05 3.247895e+10 13
  39. ####################
  40. # COMB_3
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 2
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda2_impl0 (Comb3)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 617e5fe6 7372800 0.000000e+00 5.552387e+04 5.714037e+03 1.054954e+06 5.919546e+10 19
  68. cea37d6d 819200 0.000000e+00 9.707597e+03 9.439210e+02 9.707597e+04 9.512842e+08 10
  69. afdd228b 3276800 0.000000e+00 2.633937e+04 3.608518e+03 3.950905e+05 1.060175e+10 15
  70. ####################
  71. # COMB_1
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 0
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda0_impl0 (Comb1)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 617e5fe6 7372800 0.000000e+00 5.675882e+04 6.232185e+03 1.248694e+06 7.172888e+10 22
  99. cea37d6d 819200 0.000000e+00 9.541018e+03 9.285702e+02 9.541018e+04 9.189326e+08 10
  100. afdd228b 3276800 0.000000e+00 2.651477e+04 2.554649e+03 3.181772e+05 8.514711e+09 12
  101. ####################
  102. # COMB_2
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 1
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda1_impl0 (Comb2)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 617e5fe6 7372800 0.000000e+00 5.624387e+04 5.549003e+03 8.436581e+05 4.791247e+10 15
  130. cea37d6d 819200 0.000000e+00 9.661577e+03 7.114114e+02 9.661577e+04 9.385217e+08 10
  131. afdd228b 3276800 0.000000e+00 2.574090e+04 2.071791e+03 5.148179e+05 1.333772e+10 20
  132. ####################
  133. # COMB_0
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 3
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda3_impl0 (Comb0)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 617e5fe6 7372800 0.000000e+00 5.895007e+04 8.369498e+03 7.663509e+05 4.608707e+10 13
  161. cea37d6d 819200 0.000000e+00 9.910778e+03 1.200981e+03 9.910778e+04 9.966588e+08 10
  162. afdd228b 3276800 0.000000e+00 2.572979e+04 2.095041e+03 5.917851e+05 1.532746e+10 23