starpu_dgemm_gemm.sirocco 4.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda0_impl0 (Comb0)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 492beed5 66355200 7.077888e+09 6.467396e+03 5.820387e+02 1.403425e+06 9.150018e+09 217
  37. 0b0b0ce8 7372800 2.621440e+08 2.828637e+02 4.132770e+01 2.376055e+04 6.864469e+06 84
  38. 4220e23d 29491200 2.097152e+09 2.091138e+03 2.430963e+02 3.764048e+05 7.977516e+08 180
  39. ####################
  40. # COMB_2
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 3
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda3_impl0 (Comb2)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. 492beed5 66355200 7.077888e+09 6.530201e+03 6.982602e+02 1.214617e+06 8.022384e+09 186
  68. 0b0b0ce8 7372800 2.621440e+08 2.596160e+02 3.720670e+01 2.907699e+04 7.703898e+06 112
  69. 4220e23d 29491200 2.097152e+09 2.068075e+03 2.561461e+02 4.156832e+05 8.728519e+08 201
  70. ####################
  71. # COMB_3
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 1
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda1_impl0 (Comb3)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. 492beed5 66355200 7.077888e+09 6.594324e+03 6.341124e+02 1.384808e+06 9.216313e+09 210
  99. 0b0b0ce8 7372800 2.621440e+08 2.592059e+02 3.728165e+01 2.773503e+04 7.337807e+06 107
  100. 4220e23d 29491200 2.097152e+09 2.149687e+03 2.853500e+02 3.847940e+05 8.417616e+08 179
  101. ####################
  102. # COMB_1
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 2
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda2_impl0 (Comb1)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. 492beed5 66355200 7.077888e+09 6.615698e+03 6.959563e+02 1.210673e+06 8.098082e+09 183
  130. 0b0b0ce8 7372800 2.621440e+08 2.665077e+02 3.721734e+01 3.278045e+04 8.906615e+06 123
  131. 4220e23d 29491200 2.097152e+09 2.090283e+03 2.730830e+02 4.285080e+05 9.109906e+08 205
  132. ####################
  133. # COMB_4
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 0
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cpu0_impl0 (Comb4)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. 492beed5 66355200 7.077888e+09 2.793361e+05 4.545353e+04 2.039154e+07 5.846913e+12 73
  161. 0b0b0ce8 7372800 2.621440e+08 1.003329e+04 9.763114e+02 3.471519e+06 3.516056e+10 346
  162. 4220e23d 29491200 2.097152e+09 8.266143e+04 1.577004e+04 6.860899e+06 5.877733e+11 83