starpu_slu_lu_model_22.idgraf 8.7 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_8
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb8)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. d46431bb 1228800 0.000000e+00 3.393927e+03 8.566524e+01 3.533078e+06 1.199865e+10 1041
  37. f0ac7beb 4915200 0.000000e+00 2.682238e+04 4.332821e+02 9.951104e+06 2.669820e+11 371
  38. 24c84a50 11059200 0.000000e+00 8.930213e+04 1.450773e+03 2.679064e+07 2.393092e+12 300
  39. ####################
  40. # COMB_5
  41. # number of types devices
  42. 1
  43. ####################
  44. # DEV_0
  45. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  46. 1
  47. ####################
  48. # DEV_0
  49. # device id
  50. 1
  51. ####################
  52. # DEV_0
  53. # number of cores
  54. 1
  55. ##########
  56. # number of implementations
  57. 1
  58. #####
  59. # Model for cuda1_impl0 (Comb5)
  60. # number of entries
  61. 3
  62. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  63. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  64. # a b c
  65. nan nan nan
  66. # hash size flops mean (us) dev (us) sum sum2 n
  67. d46431bb 1228800 0.000000e+00 1.946363e+02 2.537099e+01 6.294539e+05 1.245963e+08 3234
  68. f0ac7beb 4915200 0.000000e+00 9.257288e+02 6.590058e+01 3.791785e+06 3.527953e+09 4096
  69. 24c84a50 11059200 0.000000e+00 2.991139e+03 1.645886e+02 1.221282e+07 3.664085e+10 4083
  70. ####################
  71. # COMB_0
  72. # number of types devices
  73. 1
  74. ####################
  75. # DEV_0
  76. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  77. 1
  78. ####################
  79. # DEV_0
  80. # device id
  81. 4
  82. ####################
  83. # DEV_0
  84. # number of cores
  85. 1
  86. ##########
  87. # number of implementations
  88. 1
  89. #####
  90. # Model for cuda4_impl0 (Comb0)
  91. # number of entries
  92. 3
  93. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  94. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  95. # a b c
  96. nan nan nan
  97. # hash size flops mean (us) dev (us) sum sum2 n
  98. d46431bb 1228800 0.000000e+00 1.954243e+02 2.831383e+01 5.661443e+05 1.129608e+08 2897
  99. f0ac7beb 4915200 0.000000e+00 9.376794e+02 7.341921e+01 3.415966e+06 3.222718e+09 3643
  100. 24c84a50 11059200 0.000000e+00 2.995872e+03 1.614697e+02 1.133938e+07 3.407000e+10 3785
  101. ####################
  102. # COMB_1
  103. # number of types devices
  104. 1
  105. ####################
  106. # DEV_0
  107. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  108. 1
  109. ####################
  110. # DEV_0
  111. # device id
  112. 6
  113. ####################
  114. # DEV_0
  115. # number of cores
  116. 1
  117. ##########
  118. # number of implementations
  119. 1
  120. #####
  121. # Model for cuda6_impl0 (Comb1)
  122. # number of entries
  123. 3
  124. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  125. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  126. # a b c
  127. nan nan nan
  128. # hash size flops mean (us) dev (us) sum sum2 n
  129. d46431bb 1228800 0.000000e+00 1.867261e+02 2.556099e+01 5.342234e+05 1.016227e+08 2861
  130. f0ac7beb 4915200 0.000000e+00 8.996740e+02 6.639270e+01 3.427758e+06 3.100659e+09 3810
  131. 24c84a50 11059200 0.000000e+00 2.987519e+03 1.530428e+02 1.113747e+07 3.336072e+10 3728
  132. ####################
  133. # COMB_3
  134. # number of types devices
  135. 1
  136. ####################
  137. # DEV_0
  138. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  139. 1
  140. ####################
  141. # DEV_0
  142. # device id
  143. 0
  144. ####################
  145. # DEV_0
  146. # number of cores
  147. 1
  148. ##########
  149. # number of implementations
  150. 1
  151. #####
  152. # Model for cuda0_impl0 (Comb3)
  153. # number of entries
  154. 3
  155. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  156. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  157. # a b c
  158. nan nan nan
  159. # hash size flops mean (us) dev (us) sum sum2 n
  160. d46431bb 1228800 0.000000e+00 1.927028e+02 2.478568e+01 6.783137e+05 1.328754e+08 3520
  161. f0ac7beb 4915200 0.000000e+00 9.234475e+02 6.432680e+01 3.846159e+06 3.568960e+09 4165
  162. 24c84a50 11059200 0.000000e+00 2.982449e+03 1.542480e+02 1.210278e+07 3.619247e+10 4058
  163. ####################
  164. # COMB_2
  165. # number of types devices
  166. 1
  167. ####################
  168. # DEV_0
  169. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  170. 1
  171. ####################
  172. # DEV_0
  173. # device id
  174. 5
  175. ####################
  176. # DEV_0
  177. # number of cores
  178. 1
  179. ##########
  180. # number of implementations
  181. 1
  182. #####
  183. # Model for cuda5_impl0 (Comb2)
  184. # number of entries
  185. 3
  186. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  187. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  188. # a b c
  189. nan nan nan
  190. # hash size flops mean (us) dev (us) sum sum2 n
  191. d46431bb 1228800 0.000000e+00 1.868734e+02 2.558187e+01 5.049318e+05 9.612659e+07 2702
  192. f0ac7beb 4915200 0.000000e+00 9.407115e+02 6.874274e+01 3.317889e+06 3.137844e+09 3527
  193. 24c84a50 11059200 0.000000e+00 2.972987e+03 1.569773e+02 1.177600e+07 3.510750e+10 3961
  194. ####################
  195. # COMB_6
  196. # number of types devices
  197. 1
  198. ####################
  199. # DEV_0
  200. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  201. 1
  202. ####################
  203. # DEV_0
  204. # device id
  205. 3
  206. ####################
  207. # DEV_0
  208. # number of cores
  209. 1
  210. ##########
  211. # number of implementations
  212. 1
  213. #####
  214. # Model for cuda3_impl0 (Comb6)
  215. # number of entries
  216. 3
  217. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  218. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  219. # a b c
  220. nan nan nan
  221. # hash size flops mean (us) dev (us) sum sum2 n
  222. d46431bb 1228800 0.000000e+00 1.924732e+02 2.459364e+01 6.245755e+05 1.221768e+08 3245
  223. f0ac7beb 4915200 0.000000e+00 9.173887e+02 7.039530e+01 3.781476e+06 3.489510e+09 4122
  224. 24c84a50 11059200 0.000000e+00 3.001859e+03 1.612679e+02 1.156916e+07 3.482922e+10 3854
  225. ####################
  226. # COMB_4
  227. # number of types devices
  228. 1
  229. ####################
  230. # DEV_0
  231. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  232. 1
  233. ####################
  234. # DEV_0
  235. # device id
  236. 7
  237. ####################
  238. # DEV_0
  239. # number of cores
  240. 1
  241. ##########
  242. # number of implementations
  243. 1
  244. #####
  245. # Model for cuda7_impl0 (Comb4)
  246. # number of entries
  247. 3
  248. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  249. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  250. # a b c
  251. nan nan nan
  252. # hash size flops mean (us) dev (us) sum sum2 n
  253. d46431bb 1228800 0.000000e+00 1.877972e+02 2.764994e+01 5.324050e+05 1.021516e+08 2835
  254. f0ac7beb 4915200 0.000000e+00 9.245688e+02 6.946750e+01 3.363581e+06 3.127419e+09 3638
  255. 24c84a50 11059200 0.000000e+00 3.005524e+03 1.690713e+02 1.154422e+07 3.480621e+10 3841
  256. ####################
  257. # COMB_7
  258. # number of types devices
  259. 1
  260. ####################
  261. # DEV_0
  262. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  263. 1
  264. ####################
  265. # DEV_0
  266. # device id
  267. 2
  268. ####################
  269. # DEV_0
  270. # number of cores
  271. 1
  272. ##########
  273. # number of implementations
  274. 1
  275. #####
  276. # Model for cuda2_impl0 (Comb7)
  277. # number of entries
  278. 3
  279. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  280. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  281. # a b c
  282. nan nan nan
  283. # hash size flops mean (us) dev (us) sum sum2 n
  284. d46431bb 1228800 0.000000e+00 1.865351e+02 2.381101e+01 6.651841e+05 1.261020e+08 3566
  285. f0ac7beb 4915200 0.000000e+00 9.257403e+02 6.896157e+01 3.669635e+06 3.415980e+09 3964
  286. 24c84a50 11059200 0.000000e+00 3.007743e+03 1.477912e+02 1.238889e+07 3.735258e+10 4119