starpu_dlu_lu_model_22.sirocco 5.4 KB

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  1. ##################
  2. # Performance Model Version
  3. 44
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 5
  8. ####################
  9. # COMB_0
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 2
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda2_impl0 (Comb0)
  29. # number of entries
  30. 4
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # hash size flops mean (us) dev (us) sum sum2 n
  36. 24c84a50 22118400 0.000000e+00 1.754881e+03 1.567907e+02 8.516439e+06 1.506464e+10 4853
  37. d46431bb 2457600 0.000000e+00 9.227862e+01 1.339393e+01 6.585925e+05 6.205436e+07 7137
  38. f0ac7beb 9830400 0.000000e+00 5.560171e+02 4.481480e+01 2.452035e+06 1.372230e+09 4410
  39. 8cfc3ba0 49766400 0.000000e+00 5.688840e+03 4.278238e+02 1.962081e+07 1.122509e+11 3449
  40. ####################
  41. # COMB_3
  42. # number of types devices
  43. 1
  44. ####################
  45. # DEV_0
  46. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  47. 1
  48. ####################
  49. # DEV_0
  50. # device id
  51. 3
  52. ####################
  53. # DEV_0
  54. # number of cores
  55. 1
  56. ##########
  57. # number of implementations
  58. 1
  59. #####
  60. # Model for cuda3_impl0 (Comb3)
  61. # number of entries
  62. 4
  63. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  64. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  65. # a b c
  66. nan nan nan
  67. # hash size flops mean (us) dev (us) sum sum2 n
  68. 24c84a50 22118400 0.000000e+00 1.725012e+03 1.556789e+02 8.775134e+06 1.526049e+10 5087
  69. d46431bb 2457600 0.000000e+00 9.099306e+01 1.290433e+01 7.117477e+05 6.606663e+07 7822
  70. f0ac7beb 9830400 0.000000e+00 5.497124e+02 4.364744e+01 2.308242e+06 1.276869e+09 4199
  71. 8cfc3ba0 49766400 0.000000e+00 5.591076e+03 4.188165e+02 1.997692e+07 1.123192e+11 3573
  72. ####################
  73. # COMB_2
  74. # number of types devices
  75. 1
  76. ####################
  77. # DEV_0
  78. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  79. 1
  80. ####################
  81. # DEV_0
  82. # device id
  83. 0
  84. ####################
  85. # DEV_0
  86. # number of cores
  87. 1
  88. ##########
  89. # number of implementations
  90. 1
  91. #####
  92. # Model for cuda0_impl0 (Comb2)
  93. # number of entries
  94. 4
  95. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  96. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  97. # a b c
  98. nan nan nan
  99. # hash size flops mean (us) dev (us) sum sum2 n
  100. 24c84a50 22118400 0.000000e+00 1.724207e+03 1.559700e+02 8.529651e+06 1.482723e+10 4947
  101. d46431bb 2457600 0.000000e+00 9.395983e+01 1.410875e+01 5.884704e+05 5.653928e+07 6263
  102. f0ac7beb 9830400 0.000000e+00 5.531811e+02 3.935565e+01 3.264875e+06 1.815209e+09 5902
  103. 8cfc3ba0 49766400 0.000000e+00 5.682607e+03 4.627422e+02 2.006529e+07 1.147792e+11 3531
  104. ####################
  105. # COMB_4
  106. # number of types devices
  107. 1
  108. ####################
  109. # DEV_0
  110. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  111. 0
  112. ####################
  113. # DEV_0
  114. # device id
  115. 0
  116. ####################
  117. # DEV_0
  118. # number of cores
  119. 1
  120. ##########
  121. # number of implementations
  122. 1
  123. #####
  124. # Model for cpu0_impl0 (Comb4)
  125. # number of entries
  126. 4
  127. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  128. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  129. # a b c
  130. nan nan nan
  131. # hash size flops mean (us) dev (us) sum sum2 n
  132. 24c84a50 22118400 0.000000e+00 6.659236e+04 1.142300e+04 1.507651e+08 1.033522e+13 2264
  133. d46431bb 2457600 0.000000e+00 3.623237e+03 8.721045e+02 1.668138e+07 6.394225e+10 4604
  134. f0ac7beb 9830400 0.000000e+00 2.355764e+04 4.984182e+03 4.405279e+07 1.084235e+12 1870
  135. 8cfc3ba0 49766400 0.000000e+00 2.164742e+05 3.673582e+04 3.325044e+08 7.405148e+13 1536
  136. ####################
  137. # COMB_1
  138. # number of types devices
  139. 1
  140. ####################
  141. # DEV_0
  142. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3, SCC - 4)
  143. 1
  144. ####################
  145. # DEV_0
  146. # device id
  147. 1
  148. ####################
  149. # DEV_0
  150. # number of cores
  151. 1
  152. ##########
  153. # number of implementations
  154. 1
  155. #####
  156. # Model for cuda1_impl0 (Comb1)
  157. # number of entries
  158. 4
  159. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  160. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  161. # a b c
  162. nan nan nan
  163. # hash size flops mean (us) dev (us) sum sum2 n
  164. 24c84a50 22118400 0.000000e+00 1.746747e+03 1.539679e+02 8.628932e+06 1.518967e+10 4940
  165. d46431bb 2457600 0.000000e+00 9.539483e+01 1.447066e+01 7.032507e+05 6.863017e+07 7372
  166. f0ac7beb 9830400 0.000000e+00 5.601014e+02 3.783630e+01 3.218342e+06 1.810824e+09 5746
  167. 8cfc3ba0 49766400 0.000000e+00 5.710157e+03 4.302245e+02 2.027106e+07 1.164080e+11 3550